Abstract: The invention relates to a memory buffer, a method for operating the memory buffer, a memory module with a memory buffer, a testing method for the memory module, and an operating method for the memory module. The memory buffer comprises at least one memory logic unit that is connected with at least one memory-side bus system and with at least one host-side bus system, and that is characterized in that at least one redundancy memory is further available, so that a comparison of at least one memory cell address of said memory logic unit with at least one further memory cell address can be performed, and a transmission of at least one bus signal can be switched between said memory-side bus system and said redundancy memory on the basis of the comparison.

Abstract: A calibration device for the calibration of a tester channel of a tester device is provided. The calibration device includes a connecting device and a planar contact carrier with a first contact area and a second contact area insulated from the first contact area, the first contact area being generally surrounded by the second contact area, so that, when a needle card connected to the tester device is placed onto the contact carrier of the calibration device, one of the contact-connecting needles of the needle card which is connected to the tester channel to be calibrated is placed onto the first contact area and a plurality or all of the further contact-connecting needles of the needle card at tester channels that are not to be calibrated are placed onto the second contact area.

Abstract: A process and device for calibrating a semiconductor component test system includes a first connection, at which a corresponding signal, in particular a calibration signal can be input, and a second and third connection, at which the signal, in particular a calibration signal, can be emitted. The first connection is and/or can be connected via a corresponding line to a first switching apparatus, which is and/or can be connected to the second connection. A second switching apparatus is and/or can be connected to the third connection. Advantageously, the signal is then transferred to the second connection, and barred from the third connection by the first switching apparatus being closed and the second switching apparatus being opened.

Abstract: An integrated semiconductor memory device includes a control circuit with a mode register to store operating parameters, as well as further registers to store further operating parameters. An operating parameter is selectively written to or read from one of the registers for storage of an operating parameter as a function of a first or second state of a configuration signal that is applied to an address connection. Any subsequent write and read access to one of the registers for storage of an operating parameter takes place analogously to a write and read access to a memory cell in a memory cell array. The integrated semiconductor memory device is thus operated to allow writing and reading of operating parameters using a standard interface and a standard protocol for inputting and outputting data to and from the memory cell array.

Abstract: The invention relates to a semi-conductor component test-procedure, and a semi-conductor component test device (10b), which comprises: a device (43) for generating pseudo-random address values to be applied to corresponding address inputs of a semi-conductor component (2b), in particular a memory component, to be tested.

Abstract: The invention relates to a semi-conductor component, and a process for the in- and/or output of test data and/or semi-conductor component operating control data into or from a semi-conductor component, whereby the semi-conductor component comprises one or more useful data memory cells, and/or one or more test data and/or semi-conductor component operating control data registers for storing test data and/or semi-conductor component operating control data, and whereby the process comprises the steps of applying a control signal to the semi-conductor component, whereby the semi-conductor component is switched from a first to a second operating mode; and applying an address signal to the semi-conductor component, whereby one or more of the test data and/or semi-conductor component operating control data registers of the semi-conductor component is addressed by the address signal in the second operating mode, and one or more of the useful data memory cells in the first operating mode.

Abstract: A device and a process for the calibration of a semi-conductor component test system The invention relates to a process and a device for the calibration of a probe card and/or of a semi-conductor component test apparatus, including a first connection, at which a corresponding signal, in particular a calibration signal can be applied, and a second connection, connected or connectable with the first connection, at which the signal, in particular the calibration signal, can be emitted, and a third connection, at which a corresponding further signal, in particular a calibration signal, can be applied, and a fourth connection, connected or connectable with the third connection, at which the further signal, in particular the calibration signal, can be emitted.

Abstract: The invention relates to a semi-conductor component test procedure for a system with several memory component modules, each comprising at least one memory component with a buffer connected in series before it, whereby a test module is used for testing, which test module comprises a buffer, not however a memory component corresponding with the memory components of the memory component modules. Furthermore the invention relates to a test module to be used during a corresponding procedure, in particular to a test module, which comprises a buffer, not however a memory component corresponding with the memory components of the memory component modules.

Abstract: The invention relates to a data buffer component, as well as a semi-conductor component test procedure for testing a memory module with at least one memory component with buffer connected in series before it, whereby the process includes testing the memory modules by using data indicator or data strobe, signals, which have been chronologically advanced or retarded by a pre-determined time period in relation to the memory module during normal operation.

Abstract: One embodiment of the invention provides a standardization module for use in standardizing tester channels of a tester unit using a standardization unit for making contact with contact faces which are connected to the tester channels and for standardizing the tester channels. The standardization module has a first surface on which first contact faces are arranged in such a way that contact can be made by a contact making card of the tester unit with the first contact faces in a defined fashion. The standardization module has a second surface on which second contact faces are arranged in such a way that contact can be made with the second contact faces using the standardization unit. Each of the first contact faces is respectively connected to one of the second contact faces.

Abstract: The invention relates to a test device for testing digital semiconductor circuits at wafer level having a probe card which sends/receives digital test signals to/from a test head and distributes signal channels, carrying test signals, to the respective location on the wafer via an interposer. The interposer has a printed circuit board with contact pins on both sides, and a needle or contact stud card. Additionally, all signal channels in the test device or signal channels which carry time-critical test signals in the test device contain a respective signal amplifier, the signal amplifiers preferably being digital signal amplifiers which are mounted on the printed circuit board of the interposer.

Abstract: A method for testing a memory circuit selects each cell in a region of a cell array as a target cell and performs a test cycle which includes selecting the target cell and neighboring cells which contain at least those cells for which is cannot be ruled out that their operation causes a fault-producing interaction. A data item is written to the target cell in order to produce one of two defined states. A write signal is applied to the neighboring cells in order to produce an undefined state which lies between the two defined states. The target cell and the neighboring cells are then read and the result of the reading process is used to check whether there is any interaction between the operation of the target cell and the operation of the neighboring cells.

Abstract: The invention relates to a test apparatus for testing semi-conductor components, and to a signal testing procedure, to be used especially during the testing of semi-conductor components. A signal is applied to a connection of a semi-conductor component, a reference signal is applied at a particular voltage level to a further connection of the semi-conductor component component, the signal is compared with the reference signal, the voltage level of the reference signal is changed, and the signal is compared with the reference signal.

Abstract: One embodiment of the invention provides a calibration device for the calibration of a tester channel of a tester device to which integrated components on a substrate wafer can be contact-connected for testing with electrical signals.

Abstract: A process and device for calibrating a semiconductor component test system includes a first connection, at which a corresponding signal, in particular a calibration signal can be input, and a second and third connection, at which the signal, in particular a calibration signal, can be emitted. The first connection is and/or can be connected via a corresponding line to a first switching apparatus, which is and/or can be connected to the second connection. A second switching apparatus is and/or can be connected to the third connection. Advantageously, the signal is then transferred to the second connection, and barred from the third connection by the first switching apparatus being closed and the second switching apparatus being opened.

Abstract: For testing, a reference clock signal is applied to a first delay path having a fixed delay and a second delay path having a variable delay. The delay paths are connected to inputs of a clocked circuit to initiate data transfer and they apply a clock signal and a data signal, respectively. The variable delay is set within the range [tF−n&Dgr;t/2; tF+n&Dgr;t/2]. The fixed delay tF is at least n&Dgr;t/2. For calibration, the setting range of the variable delay and the fixed delay are each increased to the k-fold value and the variable delay is incremented in steps from n=0 until three phase changes are detected. The value of n at the first phase cycle completion corresponds to the variable delay for the set-up time and the value of n at the third phase cycle completion corresponds to the variable delay for the hold time.

Abstract: An integrated test circuit, as part of an integrated circuit, includes phase-shifted test signals fed through inputs A and B. These test signals are conducted through a plurality of cascaded delay elements, the advancing of the first test signal through the delay elements being held and evaluated by the second test signal.

Abstract: An integrated test circuit, as part of an integrated circuit, includes phase-shifted test signals fed through inputs A and B. These test signals are conducted through a plurality of cascaded delay elements, the advancing of the first test signal through the delay elements being held and evaluated by the second test signal.

Abstract: A method for testing a memory circuit selects each cell in a region of a cell array as a target cell and performs a test cycle which includes selecting the target cell and neighboring cells which contain at least those cells for which is cannot be ruled out that their operation causes a fault-producing interaction. A data item is written to the target cell in order to produce one of two defined states. A write signal is applied to the neighboring cells in order to produce an undefined state which lies between the two defined states. The target cell and the neighboring cells are then read and the result of the reading process is used to check whether there is any interaction between the operation of the target cell and the operation of the neighboring cells.

Abstract: For testing, a reference clock signal is applied to a first delay path having a fixed delay and a second delay path having a variable delay. The delay paths are connected to inputs of a clocked circuit to initiate data transfer and they apply a clock signal and a data signal, respectively. The variable delay is set within the range [tF−n&Dgr;t/2; tF+n&Dgr;t/2]. The fixed delay tF is at least n&Dgr;t/2. For calibration, the setting range of the variable delay and the fixed delay are each increased to the k-fold value and the variable delay is incremented in steps from n=0 until three phase changes are detected. The value of n at the first phase cycle completion corresponds to the variable delay for the set-up time and the value of n at the third phase cycle completion corresponds to the variable delay for the hold time.