Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.

Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.

Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face (63) of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.

Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face (63) of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.

Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44?, 45?) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1?, 52-1?, 94, 94?, 94?) overlying the substrate (60). The active transistor(s) (41?) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42?, 43?) are also formed over the front face (63) of the substrate (60). Various terminals (42-1?, 42-2?, 43-1, 43-2?,50?, 51?, 52?, 42-1?, 42-2?, etc.) of the transistor(s) (41?), capacitor(s) (42?, 43?) and inductor(s) (44?, 45?) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98?) to minimize parasitic resistance.

Abstract: A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A conductive material fills the opening. The opening has a length direction and a width direction and a first and second feature. The first feature and the second feature are spaced apart by a first length. The first feature has first width as a maximum width of the first feature, and the second feature has a second width as the maximum width of the second feature. The opening has a minimum width between the first feature and the second feature that is no more than one fifth the first length. The first width and the second width are each at least twice the minimum width.

Abstract: A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate (228) and a bottom gate (240); (b) creating first (251), second and third (252) openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate; (c) filling the first, second and third openings with a conductive material, thereby forming source (258) and drain (260) regions in the second and third openings and a conductive region (253) in the first opening; and (d) forming an electrical contact (278) to the conductive region.

Abstract: A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.

Abstract: A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.

Abstract: A toroidal inductor formed in a semiconductor substrate. Through-silicon vias are used to connect metal layers formed on top and bottom surfaces of the semiconductor substrate. In one embodiment, the vias are elongated and laid out in two concentric circles, an inner circle enclosed by an outer circle. The vias of the outer concentric circle are longer than the vias of the inner circle so that spaces between vias are the same for both circles. In another embodiment, each elongated via may include a plurality of circular vias formed in a line. Metals layers on the top and bottom of the semiconductor substrate are patterned to form wedge shaped connectors between the inner and outer vias to form the spirals of the toroidal inductor. The wedge shaped connectors with elongated vias allow spacing between spirals to be constant.

Abstract: A toroidal inductor formed in a semiconductor substrate. Through-silicon vias are used to connect metal layers formed on top and bottom surfaces of the semiconductor substrate. In one embodiment, the vias are elongated and laid out in two concentric circles, an inner circle enclosed by an outer circle. The vias of the outer concentric circle are longer than the vias of the inner circle so that spaces between vias are the same for both circles. In another embodiment, each elongated via may include a plurality of circular vias formed in a line. Metals layers on the top and bottom of the semiconductor substrate are patterned to form wedge shaped connectors between the inner and outer vias to form the spirals of the toroidal inductor. The wedge shaped connectors with elongated vias allow spacing between spirals to be constant.

Abstract: A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.

Abstract: A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A conductive material fills the opening. The opening has a length direction and a width direction and a first and second feature. The first feature and the second feature are spaced apart by a first length. The first feature has first width as a maximum width of the first feature, and the second feature has a second width as the maximum width of the second feature. The opening has a minimum width between the first feature and the second feature that is no more than one fifth the first length. The first width and the second width are each at least twice the minimum width.

Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44?, 45?) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1?, 52-1?, 94, 94?, 94?) overlying the substrate (60). The active transistor(s) (41?) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42?, 43?) are also formed over the front face (63) of the substrate (60). Various terminals (42-1?, 42-2?, 43-1, 43-2?,50?, 51?, 52?, 42-1?, 42-2?, etc.) of the transistor(s) (41?), capacitor(s) (42?, 43?) and inductor(s) (44?, 45?) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98?) to minimize parasitic resistance.

Abstract: A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer.

Abstract: A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer.

Abstract: A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate (228) and a bottom gate (240); (b) creating first (251), second and third (252) openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate; (c) filling the first, second and third openings with a conductive material, thereby forming source (258) and drain (260) regions in the second and third openings and a conductive region (253) in the first opening; and (d) forming an electrical contact (278) to the conductive region.

Abstract: A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.

Abstract: A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.

Abstract: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.