Patents by Inventor Tien-Hao Tang
Tien-Hao Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230326919Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.Type: ApplicationFiled: May 11, 2022Publication date: October 12, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
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Publication number: 20230299158Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a gate structure, a source doped region, a drain doped region, source silicide patterns, and drain silicide patterns. The gate structure is disposed on the semiconductor substrate. The source doped region and the drain doped region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction, respectively. The source silicide patterns are disposed on the source doped region. The source silicide patterns are arranged in a second direction and separated from one another. The drain silicide patterns are disposed on the drain doped region. The drain silicide patterns are arranged in the second direction and separated from one another. The source silicide patterns and the drain silicide patterns are arranged misaligned with one another in the first direction.Type: ApplicationFiled: April 12, 2022Publication date: September 21, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuan-Yu Lu, Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
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Patent number: 11257807Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.Type: GrantFiled: December 3, 2020Date of Patent: February 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20220052037Abstract: An electrostatic discharge circuit is provided. The electrostatic discharge circuit includes a cascade transistor configuration and a control circuit. The cascade transistor configuration includes a first transistor and a second transistor coupled between a power supply node and a ground node. The control circuit is coupled to the cascade transistor configuration, and coupled between the power supply node and the ground node. The control circuit includes a voltage drop circuit coupled to the power supply node and the first transistor, and an electrostatic discharge detecting circuit between the voltage drop circuit and the ground node. The electrostatic discharge detecting circuit is coupled to the first transistor and the second transistor.Type: ApplicationFiled: August 11, 2020Publication date: February 17, 2022Inventors: Teng-Chuan CHEN, Chun CHIANG, Tien-Hao TANG
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Patent number: 11189611Abstract: An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.Type: GrantFiled: April 9, 2020Date of Patent: November 30, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
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Patent number: 11004840Abstract: A silicon controlled rectifier includes a substrate, an N-type well, a P-type well, a gate structure, a first N-type doped region, a second N-type doped region, a first P-type doped region, a second P-type doped region, a first STI, and a second STI. The N-type well and the P-type well are disposed in the substrate. The gate structure is disposed on the P-type well. The first N-type doped region is disposed in the N-type well at one side of the gate structure. The second N-type doped region is disposed in the P-type well at another side of the gate structure. The first P-type doped region is disposed in the N-type well. The second P-type doped region is disposed in the P-type well. The first STI is between the first N-type and first P-type doped regions. The second STI is between the second N-type and second P-type doped regions.Type: GrantFiled: November 27, 2018Date of Patent: May 11, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Che Yen, Tien-Hao Tang, Chun Chiang, Kuan-Cheng Su
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Patent number: 10978442Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.Type: GrantFiled: June 19, 2019Date of Patent: April 13, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ying-Wei Tseng, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20210091069Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.Type: ApplicationFiled: December 3, 2020Publication date: March 25, 2021Applicant: United Microelectronics Corp.Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Patent number: 10903205Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.Type: GrantFiled: April 25, 2019Date of Patent: January 26, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Patent number: 10897131Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.Type: GrantFiled: January 24, 2018Date of Patent: January 19, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Cheng Liao, Ting-Yao Lin, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20200381415Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.Type: ApplicationFiled: June 19, 2019Publication date: December 3, 2020Inventors: Ying-Wei Tseng, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20200343238Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.Type: ApplicationFiled: April 25, 2019Publication date: October 29, 2020Applicant: United Microelectronics Corp.Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20200235088Abstract: An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.Type: ApplicationFiled: April 9, 2020Publication date: July 23, 2020Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
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Patent number: 10672759Abstract: An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other.Type: GrantFiled: September 6, 2018Date of Patent: June 2, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
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Publication number: 20200144814Abstract: A silicon controlled rectifier includes a substrate, an N-type well, a P-type well, a gate structure, a first N-type doped region, a second N-type doped region, a first P-type doped region, a second P-type doped region, a first STI, and a second STI. The N-type well and the P-type well are disposed in the substrate. The gate structure is disposed on the P-type well. The first N-type doped region is disposed in the N-type well at one side of the gate structure. The second N-type doped region is disposed in the P-type well at another side of the gate structure. The first P-type doped region is disposed in the N-type well. The second P-type doped region is disposed in the P-type well. The first STI is between the first N-type and first P-type doped regions. The second STI is between the second N-type and second P-type doped regions.Type: ApplicationFiled: November 27, 2018Publication date: May 7, 2020Inventors: Shih-Che Yen, Tien-Hao Tang, Chun Chiang, Kuan-Cheng Su
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Patent number: 10629585Abstract: An electrostatic discharge (ESD) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. The first doped region and the second doped region have a second conductivity type complementary to the first conductivity type. The drain region is electrically connected to an input/output pad. The source region is electrically connected to a ground pad. The first doped region and the second doped region are electrically connected to each other.Type: GrantFiled: May 18, 2018Date of Patent: April 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Chen Chang
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Patent number: 10546849Abstract: A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region.Type: GrantFiled: August 25, 2016Date of Patent: January 28, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Yu Huang, Hou-Jen Chiu, Tien-Hao Tang
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Patent number: 10522530Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.Type: GrantFiled: March 21, 2018Date of Patent: December 31, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun Chiang, Ying-Wei Tseng, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20190273077Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.Type: ApplicationFiled: March 21, 2018Publication date: September 5, 2019Inventors: Chun Chiang, Ying-Wei Tseng, Ping-Chen Chang, Tien-Hao Tang
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Patent number: 10366978Abstract: A grounded gate NMOS transistor includes a P-type substrate, P-well region in the P-type substrate, and a gate finger traversing the P-well region. The gate finger has a first spacer on a first sidewall and a second spacer on a second sidewall opposite to the first sidewall. An N+ drain doping region is disposed in the P-type substrate and is adjacent to the first sidewall of the gate finger. The N+ drain doping region is contiguous with a bottom edge of the first spacer. An N+ source doping region is disposed in the P-type substrate opposite to the N+ drain doping region. The N+ source doping region is kept a predetermined distance from a bottom edge of the second spacer. A P+ pick-up ring is disposed in the P-well region and surrounds the gate finger, the N+ drain doping region, and the N+ source doping region.Type: GrantFiled: July 16, 2018Date of Patent: July 30, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Hsiang Chang, Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su