Abstract: Processing of prefetched data based on cache residency. Data to be used in future processing is prefetched. A block of data being prefetched is selected for processing, and a check is made as to whether the block of data is resident in a selected cache (e.g., L1 cache). If the block of data is resident in the selected cache, it is processed; otherwise, processing is bypassed until a later time when it is resident in the selected cache.

Abstract: A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include user-specified information that may facilitate debugging of an aborted transaction.

Abstract: A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include user-specified information that may facilitate debugging of an aborted transaction.

Abstract: One aspect is an analysis system that includes a processor operably coupled to a memory and configured to perform a method. The method includes defining a set of workloads for a targeted multi-core computer system based on a plurality of metrics of interest to profile. A plurality of workload-to-core mappings is generated for the workloads on the targeted multi-core computer system. The workloads run on the targeted multi-core computer system based on the workload-to-core mappings to produce a mapping of the workloads to the metrics of interest as experimental data. A statistical analysis is applied on the experimental data to define a plurality of metric profiles for the targeted multi-core computer system.

Abstract: Transient mode for an application is toggled. Transient mode for an application executing in the computing environment is activated. Based on activating transient mode for the application, a plurality of memory accesses are processed as transient accesses. Based on processing the plurality of memory accesses, transient mode for the application is deactivated.

Abstract: Embodiments relate to accessing data in a memory. A method for accessing data in a memory coupled to a processor is provided. The method receives a memory reference instruction for accessing data of a first size at an address in the memory. The method determines an alignment size of the address in the memory. The method accesses the data of the first size in one or more groups of data by accessing each group of data block concurrently. The groups of data have sizes that are multiples of the alignment size.

Abstract: An aspect includes performing, for each of a plurality of hardware threads executing on a plurality of cores in a (SMP) computer system, receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer. The value of the timer is compared to a threshold value for the hardware thread, where the threshold value specifies a number of clock cycles. Based on the value of the timer meeting the threshold value, a control signal is sent to cause all hardware threads currently executing on the core to halt execution and data describing a state of the core is logged. Each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.

Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

Abstract: Effectiveness of prefetch instructions is determined. A prefetch instruction is executed to request that data be fetched into a cache of the computing environment. The effectiveness of the prefetch instruction is determined. This includes updating, based on executing the prefetch instruction, a cache directory of the cache. The updating includes, in the cache directory, effectiveness data relating to the data. The effectiveness data includes whether the data was installed in the cache based on the prefetch instruction. Additionally, the determining the effectiveness includes obtaining at least a portion of the effectiveness data from the cache directory, and using the at least a portion of effectiveness data to determine the effectiveness of the prefetch instruction.

Abstract: A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

Abstract: A query is performed to obtain cache residency and/or other information regarding selected data. The data to be queried is data of a cache line, prefetched or otherwise. The capability includes a Query Cache instruction that obtains cache residency information and/or other information and returns an indication of the requested information.

Abstract: Register restoration or register reloading is selected. A restoration request to restore a plurality of architected registers is obtained. A determination is made as to whether a snapshot associated with the plurality of architected registers is valid. The snapshot provides in-core values for the plurality of architected registers. Based on the snapshot being valid, a determination is made as to whether the snapshot is to be used to recover an individual architected register of the plurality of architected registers. Based on determining the snapshot is to be used, the snapshot is used to recover the individual architected register. Based on determining the snapshot is not to be used, memory is used to recover the individual architected register.

Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.

Abstract: Selective register allocation. Based on determining that an unused physical register is unavailable for allocation, a physical register to be used for allocation is chosen from a selective group of physical registers. The selective group of physical registers is associated with a snapshot of one type of snapshot selected from a plurality of types of snapshots. The snapshot maps physical registers to architected registers. The physical register chosen for allocation is allocated.

Abstract: Processing prefetch memory operations and transactions. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, determining whether a priority of the remote processor is greater than a priority of a local processor. The write prefetch request is executed in response to a to a determination that the priority of the remote processor is greater than the priority of the local processor. Prefetch data produced by execution of the prefetch request is provided to the remote processor.

Abstract: Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions.

Abstract: Sharing snapshots between restoration and recovery. A snapshot to be used for recovery and restoration is obtained. The snapshot includes restoration state for a plurality of architected registers. The plurality of architected registers includes one or more architected registers associated with an instruction to alter an execution path and one or more architected registers associated with a save request. At least one architected register of the plurality of architected registers is restored, based on a request. The request is a recovery request to recover at least one architected register associated with the instruction to alter the execution path or a restoration request to restore at least one architected register associated with the save request.

Abstract: Effectiveness of prefetch instructions is determined. A prefetch instruction is executed to request that data be fetched into a cache of the computing environment. The effectiveness of the prefetch instruction is determined. This includes updating, based on executing the prefetch instruction, a cache directory of the cache. The updating includes, in the cache directory, effectiveness data relating to the data. The effectiveness data includes whether the data was installed in the cache based on the prefetch instruction. Additionally, the determining the effectiveness includes obtaining at least a portion of the effectiveness data from the cache directory, and using the at least a portion of effectiveness data to determine the effectiveness of the prefetch instruction.

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.