Abstract: An information handling system may include a motherboard and a floating paddle card. The motherboard may include a host system comprising a host system processor, a logic device configured to perform a functionality of the information handling system in accordance with code stored on non-transitory computer-readable media of the logic device, and a management controller communicatively coupled to the host system processor and the logic device and configured to perform out-of-band management of the information handling system. The floating paddle card may be communicatively coupled to the motherboard and configured to serve as interface between one or more devices coupled to the floating paddle card and the logic device and the management controller, the floating paddle card comprising a microcontroller unit configured to, alone or in combination with other circuitry of the floating paddle card, divide management of the one or more devices between the motherboard and the floating paddle card.

Abstract: A method may be provided for a system having a logic device interfaced between a management controller and a plurality of subsystems, wherein the logic device includes a plurality of purpose-built engines, each purpose-built engine configured to perform single-wire communication with one or more subsystems in accordance with a particular protocol associated with such purpose-built engine and a purpose-built engine group switch interfaced between the plurality of purpose-built engines and a plurality of connectors for communicatively coupling the plurality of subsystems to the logic device. The method may include establishing, with a purpose-built engine group switch, a plurality of communication routes based on one or more switch control signals, wherein each route of the plurality of communication routes is established between a respective purpose-built engine and a respective connector.

Abstract: An information handling system may include a host system comprising a host system processor and a management controller communicatively coupled to the host system processor and configured to perform out-of-band management of a plurality of devices of the information handling system, and further configured to, during a powering on of the host system randomly select a subset of one or more devices of the plurality of devices for partial validation of firmware of the plurality of devices, randomly select a plurality of offsets associated with the one or more devices for partial verification of the firmware, and perform verification of the one or more devices at the plurality of offsets.

Abstract: An information handling system may include a motherboard and a floating paddle card. The motherboard may include a host system comprising a host system processor, a logic device configured to perform a functionality of the information handling system in accordance with code stored on non-transitory computer-readable media of the logic device, and a management controller communicatively coupled to the host system processor and the logic device and configured to perform out-of-band management of the information handling system. The floating paddle card may be communicatively coupled to the motherboard and configured to serve as interface between one or more devices coupled to the floating paddle card and the logic device and the management controller, the floating paddle card comprising a microcontroller unit configured to, alone or in combination with other circuitry of the floating paddle card, divide management of the one or more devices between the motherboard and the floating paddle card.

Abstract: In one embodiment, a method for managing clock synchronization for a baseboard management controller includes identifying, by a management unit of the information handling system, a real-time clock of the information handling system based on a real-time clock time value; receiving, by the management unit, a request for the real-time clock time value from the baseboard management controller; retrieving, by the management unit, the real-time clock time value from the real-time clock; sending, by the management unit, the real-time clock time value to a logic device of the information handling system; sending, by the logic device, an interrupt signal to the baseboard management controller indicating that the real-time clock time value is stored; retrieving, by the baseboard management controller, the real-time clock time value from the logic device; and updating, by the baseboard management controller, a baseboard management controller time value based on the real-time clock time value.

Abstract: An information handling system may include a host system comprising a processor and a management controller comprising a main processor and a trusted integrated processor configured to perform secured boot services and run-time security functions of the management controller. The information handling system may also include a legacy communications bus interfaced between the host system and the main processor and a secure communications bus interfaced between the host system and the main processor. The trusted integrated processor is further configured to implement a secure attestation channel to the host system via the secure communications bus in order to provide access by the host system to security services owned by the management controller.

Abstract: A system may include a controller, an endpoint device, and a cable coupled between the controller and the endpoint device and comprising a communication wire for bidirectionally communicating signals between the controller and the endpoint device and a circuit formed as a part of the cable and communicatively coupled to the communication wire, the circuit having a microcontroller unit configured to communicate identifying information regarding the cable to the controller via the communication wire and without contention with the signals bidirectionally communicated between the controller and the endpoint device.

Abstract: An information handling system may include a host system comprising a host system processor, a logic device configured to perform a functionality of the information handling system in accordance with code stored on non-transitory computer-readable media of the logic device, and a management controller communicatively coupled to the host system processor and the logic device and configured to perform out-of-band management of the information handling system. The management controller may be further configured to: during a boot of the management controller, perform an initial authentication of the code via an immutable interface of the logic device, after the initial authentication and prior to completion of boot of the management controller, enable a hardware lock to prevent write access to the logic device via the immutable interface, and in response to a power on request of the host system, perform a second authentication of the code via a mutable interface of the logic device.

Abstract: A method may be provided for a system having a logic device interfaced between a management controller and a plurality of subsystems, wherein the logic device includes a plurality of purpose-built engines, each purpose-built engine configured to perform single-wire communication with one or more subsystems in accordance with a particular protocol associated with such purpose-built engine and a purpose-built engine group switch interfaced between the plurality of purpose-built engines and a plurality of connectors for communicatively coupling the plurality of subsystems to the logic device. The method may include establishing, with a purpose-built engine group switch, a plurality of communication routes based on one or more switch control signals, wherein each route of the plurality of communication routes is established between a respective purpose-built engine and a respective connector.

Abstract: A method may include, during a first initial boot of a management controller, writing baseline processor domain status information associated with boot of each of a main processor and a second processor of the management controller to a baseline queue, and during each subsequent boot of the management controller, writing run-time processor domain status information associated with boot of each of the main processor and the second processor to a run-time queue, determining if a deviation exists between the run-time queue and the baseline queue, and responsive to the deviation existing between the run-time queue and the baseline queue, taking one or more responsive actions.

Abstract: An information handling system may include a host system comprising a host system processor and a management controller communicatively coupled to the host system processor and comprising a main processor for implementing functionality of the management controller and a co-processor communicatively coupled to the host system processor and configured to implement a proxy to the host system to enable the host system to access devices managed by the management controller.

Abstract: An information handling system may include a bus initiator, a plurality of bus endpoints, and a single-wire bus communicatively coupled between the bus initiator and the plurality of bus endpoints, wherein the bus comprises a multiplexer. The bus initiator may be configured to perform in-band addressing to select a communications channel through the multiplexer via an addressing protocol that uses pulse bursts for initiation of the addressing, identification of the communications channel, and termination of the addressing. Pulses of the pulse bursts may be sufficiently short in duration to pass through filters of the bus endpoints such that the pulse bursts are not processed by the bus endpoints.

Abstract: A system may include a controller, an endpoint device, and a cable coupled between the controller and the endpoint device and comprising a communication wire for bidirectionally communicating signals between the controller and the endpoint device and a circuit formed as a part of the cable and communicatively coupled to the communication wire, the circuit having a microcontroller unit configured to communicate identifying information regarding the cable to the controller via the communication wire and without contention with the signals bidirectionally communicated between the controller and the endpoint device.

Abstract: In accordance with one embodiment, a fan controller operates in a standard mode when main power is provided to the power supply unit in which speed of the fan is controlled in response to a primary pulse width modulation (PWM) signal from a power controller. A loss of the main power to the power supply unit may be detected at a logic circuit, which provides a secondary PWM signal to the fan controller in response to the loss of the main power. In certain embodiments, the fan controller is operated in a power loss mode in response to the secondary PWM signal to direct the speed of the fan to a low-power consumption target speed.

Abstract: An information handling system may include a memory comprising a plurality of memory modules, each memory module comprising a plurality of memory chips, a host system comprising a host system processor configured to, during a boot of the information handling system, execute a basic input/output system of the information handling system configured to monitor for one or more faults of one or more memory modules of the plurality of memory modules, and control circuitry. The control circuitry may be configured to, in response to the one or more faults, determine if, all of one or more memory modules associated with a power control signal of such one or more memory modules have experienced faults, and if all of the one or more memory modules associated with the power control signal have experienced faults, de-assert the power control signal such that the one or more memory modules are de-energized.

Abstract: An information handling system may include an air mover configured to drive a flow of air and a processing component communicatively coupled to the air mover for controlling operation of the air mover via a first wire configured to communicate analog air mover speed commands from the processing component to the air mover for controlling a speed of the air mover and a second wire configured to communicate analog tachometer information from the air mover to the processing component. At least one of the air mover and the processing component may be configured to initiate a mode for serial digital communication via the first wire and the second wire. The air mover and the processing component may be configured to communicate information to each other in accordance with a digital communication protocol via the first wire and the second wire during the mode for serial digital communication.

Abstract: A communication module may be used in an information handling system comprising an air mover configured to drive a flow of air and a processing component communicatively coupled to the air mover for controlling operation of the air mover via a first wire configured to communicate air mover speed commands from the processing component to the air mover for controlling a speed of the air mover and a second wire configured to communicate tachometer information from the air mover to the processing component. The communication module may include a connector other than an air mover connector configured to couple the air mover to the first and second wire and logic configured to monitor for an escape sequence communicated via first wire from the processing component to enter a command mode and responsive to detecting the escape sequence, communicating information regarding the air mover to the processing component via second wire.

Abstract: An information handling system may include an air mover configured to drive a flow of air and a processing component communicatively coupled to the air mover for controlling operation of the air mover via a first wire configured to communicate analog air mover speed commands from the processing component to the air mover for controlling a speed of the air mover and a second wire configured to communicate analog tachometer information from the air mover to the processing component. At least one of the air mover and the processing component may be configured to initiate a mode for serial digital communication via the first wire and the second wire. The air mover and the processing component may be configured to communicate information to each other in accordance with a digital communication protocol via the first wire and the second wire during the mode for serial digital communication.

Abstract: A method may include initializing operation of a baseboard management controller at an information handling system. The baseboard management controller includes a real time clock. The method further includes receiving clock information from a real time clock circuit included at a field programmable gate array. The clock information at the real time clock at the baseboard management controller can be updated with the clock information received from the real time clock circuit included at the field programmable gate array.

Abstract: Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.