Abstract: A method may include providing a first pulse width modulation (PWM) signal to a microcontroller unit (MCU) included at a cooling fan. The method may further include receiving information from the MCU identifying a duty cycle of a second PWM signal generated by the MCU, the duty cycle of the second PWM signal determined by the MCU based on a duty cycle of the first PWM signal and based on a tachometer signal received from a rotor included at the cooling fan. The present current consumption of the cooling fan may be determined based on the duty cycle of the second PWM signal.

Abstract: Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.

Abstract: A controller of an information handling system may detect a power fault event for one or more of a plurality of memories configured to operate in a memory mirroring mode. The controller may deactivate the one or more of the plurality of memories by mapping the one or more of the plurality of memories out from usage without rebooting the information handling system based, at least in part, on the detection of the power fault event and the received notification.

Abstract: An information handling system may include a bus initiator, a plurality of bus endpoints, and a bus communicatively coupled between the bus initiator and the plurality of bus endpoints, wherein the bus comprises a multiplexer topology of a plurality of multiplexers. The bus initiator may be configured to perform in-band addressing to select a communications channel through the multiplexer topology via an addressing protocol that uses pulse bursts for initiation of the addressing, identification of the communications channel, and termination of the addressing. Pulses of the pulse bursts may be sufficiently short in duration to pass through filters of the bus endpoints such that the pulse bursts are not processed by the endpoints.

Abstract: A system may include a first device and a second device communicatively coupled to the first device via a communications bus, wherein the communications bus comprises a single clock line for transmission of a clock signal from the first device to the second device, a single frame line for transmission of a frame alignment signal from the first device to the second device, and at least one communications channel for serialized communication of payloads of data between the first device and the second device, wherein the payloads of data have at least two different latencies.

Abstract: An information handling system may include a host system comprising a host system processor, a management controller communicatively coupled to the host system processor and a logic device and configured to perform out-of-band management of the information handling system, and a logic device communicatively coupled to the host system and the management controller. The logic device may be configured to, upon determining that a watchdog timer has timed out a threshold number of times without completion of a boot of the management controller, allow boot of the host system, after boot of the host system, determine if a later boot of the management controller occurs, and if the later boot of the management controller occurs, force the host system to power off.

Abstract: An information handling system includes a processor, a BMC, and a logic device. The BMC boots in response to an AC power cycle event, provides a BMC ready signal in response to the boot, establishes the BMC as a root of trust for the processor in response to providing the BMC ready signal, and provides a processor boot indication to the processor in response to establishing the BMC as the root of trust. The processor boots to an operating system in response to the processor boot indication instead of in response to the AC power cycle. The logic device determines that the BMC failed to provide the BMC ready signal, determines that the BMC failed to boot in response to the AC power cycle and determining that the BMC failed to provide the BMC ready signal, and provides a power-on reset signal to the BMC in response to determining that the BMC failed to boot.

Abstract: An information handling system includes a processor complex and a baseboard management controller (BMC). The processor complex provides boot status information in response to a system boot process of the processor complex. The BMC receives first boot status information from the processor complex in response to a first system boot process, compares the first boot status information to baseline status information to determine first boot status difference information, compares the first boot status difference information to baseline boot status difference information to determine that the information handling system experienced an anomaly during the first system boot process, and sends an alert that indicates that the first system boot process experienced the anomaly.

Abstract: A method may include responsive to a power event associated with an information handling system, intercepting the power event and holding a platform controller hub of the information handling system from completing the power event to prevent execution of code of a basic input/output system of the information handling system, attempting to verify image integrity of the basic input/output system, and allowing the platform controller hub to complete the power event to allow execution of the code of the basic input/output system responsive to successful verification of the image integrity of the basic input/output system.

Abstract: A method may include providing a first pulse width modulation (PWM) signal to a microcontroller unit (MCU) included at a cooling fan. The method may further include receiving information from the MCU identifying a duty cycle of a second PWM signal generated by the MCU, the duty cycle of the second PWM signal determined by the MCU based on a duty cycle of the first PWM signal and based on a tachometer signal received from a rotor included at the cooling fan. The present current consumption of the cooling fan may be determined based on the duty cycle of the second PWM signal.

Abstract: A communication module may be used in an information handling system comprising an air mover configured to drive a flow of air and a processing component communicatively coupled to the air mover for controlling operation of the air mover via a first wire configured to communicate air mover speed commands from the processing component to the air mover for controlling a speed of the air mover and a second wire configured to communicate tachometer information from the air mover to the processing component. The communication module may include a connector other than an air mover connector configured to couple the air mover to the first wire and the second wire and logic configured to monitor for an escape sequence communicated over the first wire from the processing component to enter a command mode and responsive to detecting the escape sequence, communicating information regarding the air mover to the processing component via the second wire.

Abstract: An information handling system includes a processor with an Improved Inter-Integrated Circuit (I3C) master interface, a first device with a first I3C slave interface, and a second device with a second I3C slave interface. The first I3C slave interface provides first In-Band Interrupts (IBIs) to the I3C master interface and has a first I3C address. The second I3C interface provides second IBIs to the I3C master interface and has a second I3C address. The second I3C address is higher than the first I3C address. The processor receives the first IBI, determines that the second IBIs are masked by the first Mb due to the second I3C address being higher than the first I3C address, and assigns a third I3C address to one of the first I3C slave interface and the second I3C slave interface in response to determining that the second IBIs are masked by the first IBIs.

Abstract: An information handling system includes a device, a processor, and a runtime agent. the device provides a System Management Interrupt (SMI) in response to an error on the device. The processor receives the SMI, enters a System Management Mode (SMM), and executes first interrupt handler code in SMM to provide interrupt information associated with the SMI when the SMI is associated with a non-critical error on the device, and exit SMM to a runtime mode. The runtime agent receives the interrupt information during the runtime mode to execute second interrupt handler code to service the non-critical error on the device.

Abstract: An information handling system includes a synchronizer and a module identifier. The module identifier identifies a module identification event for a module attached to the information handling system; in response to identifying the module identification event: obtains a module identifier from the module, and makes a determination that the module identifier indicates that the module is a synchronization type of module, and initiates, based on the determination, time synchronization for the information handling system with a second information handling system using the module and the synchronizer.

Abstract: An information handling system includes a processor with an Improved Inter-Integrated Circuit (I3C) master interface, a first device with a first I3C slave interface, and a second device with a second I3C slave interface. The first I3C slave interface provides first In-Band Interrupts (Mb) to the I3C master interface and has a first I3C address. The second I3C interface provides second IBIs to the I3C master interface and has a second I3C address. The second I3C address is higher than the first I3C address. The processor receives the first IBI, determines that the second IBIs are masked by the first Mb due to the second I3C address being higher than the first I3C address, and assigns a third I3C address to one of the first I3C slave interface and the second I3C slave interface in response to determining that the second IBIs are masked by the first IBIs.

Abstract: A multiplexor for an Improved Inter-Integrated Circuit (I3C) network includes a switch, a snooper, and an I3C slave module coupled to an I3C master interface. The switch selectably couples I3C busses to the I3C master interface. Each I3C bus incudes I3C slave interfaces. The selected I3C bus is the active bus, and the non-selected I3C busses are inactive buses. The snooper detects In-Band Interrupts (IBIs) from the I3C slave interfaces coupled to the inactive buses. When the snooper receives a first IBI on an inactive bus, the snooper provides an indication. The I3C slave module provides a second IBI to the I3C master interface in response to the indication.

Abstract: An information handling system includes a device, a processor, and a runtime agent. the device provides a System Management Interrupt (SMI) in response to an error on the device. The processor receives the SMI, enters a System Management Mode (SMM), and executes first interrupt handler code in SMM to provide interrupt information associated with the SMI when the SMI is associated with a non-critical error on the device, and exit SMM to a runtime mode. The runtime agent receives the interrupt information during the runtime mode to execute second interrupt handler code to service the non-critical error on the device.

Abstract: A processor/endpoint communication coupling configuration system includes a plurality of processing subsystems coupled to a multi-endpoint adapter device by a plurality of communication couplings included on at least one hardware subsystem. A communication coupling configuration engine identifies each at least one hardware subsystem, determines at least one communication coupling configuration capability of the plurality of communication couplings, and determines at least one first multi-endpoint adapter device capability of the multi-endpoint adapter device.

Abstract: A method may include initializing operation of a baseboard management controller at an information handling system. The baseboard management controller includes a real time clock. The method further includes receiving clock information from a real time clock circuit included at a field programmable gate array. The clock information at the real time clock at the baseboard management controller can be updated with the clock information received from the real time clock circuit included at the field programmable gate array.

Abstract: An information handling system includes a synchronizer and a module identifier. The module identifier identifies a module identification event for a module attached to the information handling system; in response to identifying the module identification event: obtains a module identifier from the module, and makes a determination that the module identifier indicates that the module is a synchronization type of module, and initiates, based on the determination, time synchronization for the information handling system with a second information handling system using the module and the synchronizer.