Patents by Inventor Ting Hu
Ting Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180353880Abstract: a pre-filter device capable of preventing water leakage, that includes: a connector, a water inlet channel, a plug, and a spring. The connector is connected to a water inlet tube, and is connected to the pre-filter device. The water inlet channel is disposed in the connector, and is connected to the pre-filter device. The plug is disposed in the water inlet channel, to open or close the water inlet channel. The spring is disposed between one end of the plug and the connector, the other end of the plug is connected to and acts in cooperation with the pre-filter device. When a pre-filter device capable of preventing water leakage is burst to leak out water, it is able to close the water inlet channel automatically, to avoid the problem deteriorating into flooding the entire household, to achieve timely self protection.Type: ApplicationFiled: May 30, 2018Publication date: December 13, 2018Inventors: JING-XIAN LIU, YU-TING HU
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Patent number: 10083950Abstract: A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to the manufacturing recipe. The interposer-die mapping file corresponds to an interposer wafer including interposer dies. The die stacking method also includes loading a combination setting data according to the interposer-die mapping file, and loading a top die number and a top-die ID code of a top-die mapping file according to the combination setting data and the interposer-die mapping file. The top-die ID code corresponds to a top wafer including top dies, and the top die number corresponds to one of the top dies. The die stacking method also includes disposing the one of the top dies of the top wafer on one of the interposer dies of the interposer wafer.Type: GrantFiled: December 15, 2016Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Larry Jann, Chih-Chien Chang, Po-Wen Chuang, Ming-I Chiu, Chang-Hsi Lin, Chih-Chan Li, Yi-Ting Hu
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Publication number: 20180054439Abstract: Embodiments of the present application provide a packet processing method in a Point-to-Point Protocol over Ethernet (PPPoE) authentication process and a relevant device. A first broadcast access server (BAS) exists in a broadcast domain in which a user terminal is located, the first BAS supports the PPPoE and corresponds to a first operator. The method includes receiving, by the first BAS, a PPPoE active discovery initiation (PADI) packet sent by the user terminal; and when determining that a quantity of authentication failures of the user terminal on the first BAS is greater than a preset threshold, skipping sending, by the first BAS, a PPPoE active discovery offer (PADO) packet to the user terminal in a preset period. The technical solutions in the embodiments of the present application resolve a problem that the user terminal cannot perform access because the user terminal establishes a session with the first BAS.Type: ApplicationFiled: October 27, 2017Publication date: February 22, 2018Inventors: Ting Hu, Guofeng Qian
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Publication number: 20170276797Abstract: Electronic devices and methods for providing location information are provided, of which a representative method includes: generating sensor readings corresponding to sensed motion of the electronic device; determining a reference location information; computing a GPS-fused location information based on the reference location information and the sensor readings; generating a GPS-required event based on a change of the GPS-fused location information; generating a GPS-not-required event responsive to the reference location information being determined; receiving the GPS-fused location information and one of either the GPS-required event or the GPS-not-required event; responsive to the GPS-required event being received, operating the GPS receiver in a location information-acquiring mode during which the GPS receiver generates geographical location readings; and responsive to the GPS-not-required event being received, operating the GPS receiver in a power-saving mode during which the GPS receiver is deactivated.Type: ApplicationFiled: June 12, 2017Publication date: September 28, 2017Inventors: Yun-Chia Hsieh, Kuo-Ting Hu, Yu-Kuen Tsai, Ching-Lin Hsieh, Chien-Chih Hsu
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Patent number: 9645627Abstract: A computer stick docking system and a power management method thereof are provided. The computer stick docking system includes a docking station and a computer stick device. The docking station is configured to receive a display device and a computer stick device, including a docking battery and a docking HDMI interface circuit. The computer stick device includes a computer-stick controller and a computer-stick HDMI interface circuit. The computer-stick controller is configured to load an operating system. The computer-stick HDMI interface circuit, coupled to the computer-stick controller, is configured to request battery power information of the docking battery from the docking station after it is powered on and the computer-stick HDMI interface circuit is connected to the docking station.Type: GrantFiled: April 24, 2015Date of Patent: May 9, 2017Assignee: QUANTA COMPUTER INC.Inventors: Hsin-Liang Lin, Yi-Ting Hu, Yu-Lin Hsieh, Chen-Ming Chen, Chia-Jung Fan, Hsin-Yi Cheng
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Publication number: 20170098639Abstract: A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to the manufacturing recipe. The interposer-die mapping file corresponds to an interposer wafer including interposer dies. The die stacking method also includes loading a combination setting data according to the interposer-die mapping file, and loading a top die number and a top-die ID code of a top-die mapping file according to the combination setting data and the interposer-die mapping file. The top-die ID code corresponds to a top wafer including top dies, and the top die number corresponds to one of the top dies. The die stacking method also includes disposing the one of the top dies of the top wafer on one of the interposer dies of the interposer wafer.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Larry JANN, Chih-Chien CHANG, Po-Wen CHUANG, Ming-I CHIU, Chang-Hsi LIN, Chih-Chan LI, Yi-Ting HU
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Patent number: 9599665Abstract: A method for testing a semiconductor device is disclosed. The method comprises positioning a probe card comprising a plurality of probes above the semiconductor device and moving the probe card in a vertical direction towards the semiconductor device. The plurality of probes are moving in a vertical direction towards a plurality of electrical structures of the semiconductor device until each probe of the plurality of probes has made mechanical contact with a corresponding electrical structure of the plurality of electrical structures with a minimum quantity of force. The each probe of the plurality of probes absorbs a portion of vertical overdrive after contacting their corresponding electrical structures. The probe card absorbs any remaining vertical overdrive. The vertical overdrive is a continuing vertical movement of the plurality of probes after a first probe of the plurality of probes mechanically contacts a first corresponding electrical structure.Type: GrantFiled: May 21, 2013Date of Patent: March 21, 2017Assignee: ADVANTEST CORPORATIONInventors: Ting Hu, Lakshmikanth Namburi
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Patent number: 9536814Abstract: Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device.Type: GrantFiled: February 24, 2014Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Larry Jann, Chih-Chien Chang, Po-Wen Chuang, Ming-I Chiu, Chang-Hsi Lin, Chih-Chan Li, Yi-Ting Hu
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Publication number: 20160308436Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.Type: ApplicationFiled: June 28, 2016Publication date: October 20, 2016Inventors: Chih-Ting HU, Shin-Jang SHEN, Yi-Ching LIU
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Publication number: 20160253768Abstract: The invention relates to a method for determining an integrated network loss rate in the UHV AC cross-regional electricity trading. The method includes fitting a curve relationship between integrated network loss rates and transmitting powers on the basis of theoretical calculations of the UHV AC transmission line loss, using a relational fitted curve between actual values of integrated network loss rates and transmitting powers calculated according to gateway power statistical data to perform geometrical average correction on the original curve, and making planned values of the integrated network loss rates to be closer to the actual values according to a method for determining UHV AC integrated network loss rates according to a correction curve function relation, which greatly increases fairness of the trading settlement. The method is simple and easy to implement with high accuracy, and applicable to planning and trading settlement of regular or real-time UHV AC electricity trading.Type: ApplicationFiled: May 11, 2016Publication date: September 1, 2016Inventors: TING HU, Yinya Zhang, Dongjun Yang, Shunming Bai, Jingyou Xu, Daqiang Xiao, Cong Wei
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Patent number: 9423814Abstract: A power supply apparatus and a method for supplying power are provided. The method includes: providing a first power supply for outputting a first power signal; providing a second power supply for outputting a second power signal; and selectively charging the second power supply by using the first power supply.Type: GrantFiled: January 23, 2013Date of Patent: August 23, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Ting Hu, Chun-Hsiung Hung, Wu-Chin Peng, Kuen-Long Chang, Ken-Hui Chen
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Publication number: 20160202748Abstract: A computer stick docking system and a power management method thereof are provided. The computer stick docking system includes a docking station and a computer stick device. The docking station is configured to receive a display device and a computer stick device, including a docking battery and a docking HDMI interface circuit. The computer stick device includes a computer-stick controller and a computer-stick HDMI interface circuit. The computer-stick controller is configured to load an operating system. The computer-stick HDMI interface circuit, coupled to the computer-stick controller, is configured to request battery power information of the docking battery from the docking station after it is powered on and the computer-stick HDMI interface circuit is connected to the docking station.Type: ApplicationFiled: April 24, 2015Publication date: July 14, 2016Inventors: Hsin-Liang LIN, Yi-Ting HU, Yu-Lin HSIEH, Chen-Ming CHEN, Chia-Jung FAN, Hsin-Yi CHENG
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Patent number: 9391597Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.Type: GrantFiled: November 12, 2013Date of Patent: July 12, 2016Assignee: Macronix International Co., Ltd.Inventors: Chih-Ting Hu, Shin-Jang Shen, Yi-Ching Liu
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Patent number: 9194887Abstract: An apparatus for testing electronic devices is disclosed. The apparatus includes a plurality of probes attached to a substrate; wherein each probe is capable of elastic deformation when the probe tip comes in contact with the electronic devices; each probe comprising a plurality of isolated electrical vertical interconnect accesses (vias) connecting each probe tip to the substrate, such that each probe tip of the plurality is capable of conducting an electrical current from the device under test to the substrate. The plurality of probes may form a probe comb. Also disclosed is a probe comb holder that has at least one slot where the probe comb may be disposed. A method for assembling and disassembling the probe comb and probe comb holder is also disclosed which allows for geometric alignment of individual probes.Type: GrantFiled: January 17, 2013Date of Patent: November 24, 2015Assignee: Advantest America, Inc.Inventors: Florent Cros, Lakshmi Namburi, Ting Hu
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Patent number: 9143514Abstract: A hierarchical security model for networked computer users is described. Files and resources are controlled or created by users within the network. Each user within the network has an account that is managed by a network administrator. The account specifies the user identifier and password. Users are grouped into organizations depending upon function or other organizational parameter. The groups within the network are organized hierarchically in terms of access and control privileges. Users within a higher level group may exercise access and control privileges over files or resources owned by users in a lower level group. The account for each user further specifies the group that the owner belongs to and an identifier for any higher level groups that have access privileges over the user's group. All users within a group inherit the rights and restrictions of the group.Type: GrantFiled: June 23, 2014Date of Patent: September 22, 2015Assignee: Ellie Mae, Inc.Inventors: Limin Hu, Ting-Hu Wu, Ching-Chih Jason Han
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Publication number: 20150243630Abstract: Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device.Type: ApplicationFiled: February 24, 2014Publication date: August 27, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Larry JANN, Chih-Chien CHANG, Po-Wen CHUANG, Ming-I CHIU, Chang-Hsi LIN, Chih-Chan LI, Yi-Ting HU
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Publication number: 20150200118Abstract: A bonding apparatus includes a wafer stage, a first chip stage, a first transporting device, a second stage and a second transporting device. The wafer stage is used for holding a wafer. The first chip stage is used for holding at least one first chip. The first transporting device is used for transporting the first chip from the first chip stage onto the wafer. The second chip stage is used for holding at least one second chip. The second transporting device is used for transporting the second chip from the second chip stage onto the wafer.Type: ApplicationFiled: January 16, 2014Publication date: July 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Shan WU, Yi-Ting HU, Ming-Tan LEE, Yu-Lin WANG, Yuh-Sen CHANG, Pin-Yi SHIN, Wen-Ming CHEN, Wei-Chih CHEN, Chih-Yuan CHIU
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Publication number: 20150131344Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.Type: ApplicationFiled: November 12, 2013Publication date: May 14, 2015Applicant: Macronix International Co., Ltd.Inventors: Chih-Ting Hu, Shin-Jang Shen, Yi-Ching Liu
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Patent number: 9030577Abstract: Image processing methods and systems for handheld devices are provided. First, an image effect is determined. Then, a plurality of preview images is continuously captured by an image capture unit of an electronic device. After the respective preview image is captured, the image effect is applied to the preview image, and the preview image applied with the image effect is displayed in a display unit of the electronic device.Type: GrantFiled: January 30, 2014Date of Patent: May 12, 2015Assignee: HTC CorporationInventors: Huei-Long Wang, Bing-Sheng Lin, Ting-Ting Hu
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Patent number: 9000793Abstract: An apparatus for testing electronic devices is disclosed. The apparatus includes a plurality of probes attached to a substrate; each probe capable of elastic deformation when the probe tip comes in contact with the electronic; each probe comprising a plurality of isolated electrical vertical interconnected accesses (vias) connecting each probe tip to the substrate, such that each probe tip of the plurality is capable of conducting an electrical current from the device under test to the substrate. The plurality of probes may form a probe comb. Also disclosed is a probe comb holder that has at least one slot where the probe comb may be disposed. A method for assembling and disassembling the probe comb and probe comb holder is also disclosed which allows for geometric alignment of individual probes.Type: GrantFiled: January 17, 2013Date of Patent: April 7, 2015Assignee: Advantest America, Inc.Inventors: Florent Cros, Lakshmi Namburi, Ting Hu