Patents by Inventor To V. Pham

To V. Pham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150208510
    Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Perry H. Pelley, Michael B. McShane, Tim V. Pham
  • Patent number: 9087702
    Abstract: Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: July 21, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tim V. Pham, Michael B. McShane, Perry H. Pelley, Andrew C. Russell, James R. Guajardo
  • Patent number: 9070657
    Abstract: An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: June 30, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tim V. Pham, Derek S. Swanson, Trent S. Uehling
  • Publication number: 20150155017
    Abstract: A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.
    Type: Application
    Filed: November 29, 2013
    Publication date: June 4, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Bradley J. Garni, Huy Van V. Pham, Glenn E. Starnes, Mark Jetton, Thomas W. Liston
  • Publication number: 20150115474
    Abstract: A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Inventors: TIM V. PHAM, MICHAEL B. MCSHANE, PERRY H. PELLEY, TAB A. STEPHENS
  • Publication number: 20150097280
    Abstract: An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Inventors: Tim V. Pham, Derek S. Swanson, Trent S. Uehling
  • Publication number: 20150084168
    Abstract: A microelectronic device package including a package substrate, microelectronic component disposed on a first surface of a first portion of the substrate, and encapsulant material surrounding the microelectronic electronic component. An exposed surface of the first portion of the substrate is exposed through an opening in a first major surface of the encapsulant material. The exposed surface of the first portion has an edge. Encapsulant material is adjacent to the edge at the first major surface. The exposed surface is opposite the first surface. A stress relief feature located in one of the first major surface or a second major surface of the encapsulant material. The second major surface is opposite the first major surface. The stress relief feature reduces an amount of the encapsulant material and is 1 mm or less of a plane of the edge of the exposed surface. The plane is generally perpendicular to the exposed surface.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Inventors: MIN DING, Tim V. Pham
  • Publication number: 20150069624
    Abstract: Recessed semiconductor die stacks. In some embodiments, a semiconductor device includes a first die including an active side and a back side, the back side including a non-recessed portion thicker than a recessed portion, the recessed portion including one or more through-die vias on a recessed surface; and a second die located in the recessed portion, the second die including an active side facing the recessed surface of the first die and coupled thereto through the one or more through-die vias. In another embodiment, a method includes creating a recess on a first die having a first thickness, the recess having a depth smaller than the first thickness; coupling a second die having a second thickness greater than the depth to the recess; and reducing the thickness of the second die by an amount equal to or greater than a difference between the second thickness and the depth.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Tim V. Pham, Fonzell D. Martin, Derek S. Swanson
  • Patent number: 8976526
    Abstract: In an embodiment, a medium voltage drive system includes a transformer, multiple power cubes each coupled to the transformer, and a manifold assembly. Each power cube includes cold plates each coupled to a corresponding switching device of the cube, an inlet port in communication with a first one of the cold plates and an outlet port in communication with a last one of the cold plates. The manifold assembly can support an inlet conduit and an outlet conduit and further support first and second connection members to enable blind mating of each of the first connection members to the inlet port of one of the power cubes and each of the second connection members to the outlet port of one of the power cubes to enable two phase cooling of the plurality of power cubes.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: March 10, 2015
    Assignee: TECO-Westinghouse Motor Company
    Inventors: Devdatta P. Kulkarni, Thomas Keister, Manzoor Hussain, Scott Simmons, Ut V. Pham, Rose Craft, Randall Pipho
  • Publication number: 20150061097
    Abstract: Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 5, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Tim V. Pham, Michael B. McShane, Perry H. Pelley, Andrew C. Russell, James R. Guajardo
  • Patent number: 8970026
    Abstract: A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: George R. Leal, Leo M. Higgins, III, Tim V. Pham
  • Patent number: 8957510
    Abstract: A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: February 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tim V. Pham, James R. Guajardo, Michael B. McShane
  • Publication number: 20150008567
    Abstract: A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 8, 2015
    Inventors: TIM V. PHAM, James R. Guajardo, Michael B. Mcshane
  • Publication number: 20140345861
    Abstract: The present disclosure relates to a particularly effective well configuration that can be used for SAGD and other steam based oil recovery methods. Fishbone multilateral wells are combined with SAGD, effectively expanding steam coverage. Preferably, an array of overlapping fishbone wells cover the pay, reducing water use and allowing more complete production of the pay.
    Type: Application
    Filed: February 5, 2014
    Publication date: November 27, 2014
    Applicants: Total E&P Canada, Ltd., ConocoPhillips Surmont Partnership, ConocoPhillips Canada Resources Corp.
    Inventors: John L. STALDER, Son V. PHAM
  • Publication number: 20140306336
    Abstract: A fluid cooled semiconductor die package includes a package support substrate with a die mounting surface and an opposite package mounting surface. The package support substrate has external connector solder deposits on respective external connector pads of the package mounting surface, and a package fluid inlet duct and a package fluid outlet duct each providing fluid communication between the die mounting surface and package mounting surface. A semiconductor die is mounted on the die mounting surface. The die has external terminals electrically connected to the external connector pads. An inlet solder deposit is soldered to an inlet pad of the package mounting surface. The inlet pad surrounds an entrance of the fluid inlet duct. An outlet solder deposit is soldered to an outlet pad of the package mounting surface. The outlet pad surrounds an exit of the package fluid inlet duct.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 16, 2014
    Inventors: Chee Seng Foong, Tim V. Pham
  • Patent number: 8860212
    Abstract: A fluid cooled semiconductor die package includes a package support substrate with a die mounting surface and an opposite package mounting surface. The package support substrate has external connector solder deposits on respective external connector pads of the package mounting surface, and a package fluid inlet duct and a package fluid outlet duct each providing fluid communication between the die mounting surface and package mounting surface. A semiconductor die is mounted on the die mounting surface. The die has external terminals electrically connected to the external connector pads. An inlet solder deposit is soldered to an inlet pad of the package mounting surface. The inlet pad surrounds an entrance of the fluid inlet duct. An outlet solder deposit is soldered to an outlet pad of the package mounting surface. The outlet pad surrounds an exit of the package fluid inlet duct.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: October 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chee Seng Foong, Tim V. Pham
  • Publication number: 20140225268
    Abstract: A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.
    Type: Application
    Filed: February 12, 2013
    Publication date: August 14, 2014
    Inventors: GEORGE R. LEAL, Leo M. Higgins, III, Tim V. Pham
  • Patent number: 8798607
    Abstract: Embodiments of the present invention provide for synchronizing contact and calendar information between a handset and a computer. For example, one method as disclosed herein allows the handset to import contact and calendar information from the computing device or to export the contact and the calendar information to the computing device. The computing device can be a PC or a new handset, for example. The importation and the exportation of the contact and calendar information includes a conversion process that occurs within the handset that transforms the contact and calendar information into a format suitable for the destination of the data.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: August 5, 2014
    Assignee: KYOCERA Corporation
    Inventors: Diego Kaplan, Larry P. Nolen, Thinh V. Pham, Jonathan Wine
  • Publication number: 20140077352
    Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventors: George R. Leal, Tim V. Pham
  • Patent number: 8673357
    Abstract: This invention provides methods of spray drying pharmaceutical powders from a vibrating nozzle at low pressures. The method can effectively spray dry thick or viscous solutions or suspensions to provide small uniform particles. The invention includes dry particle compositions prepared by methods of low pressure spraying from vibrating nozzles.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 18, 2014
    Assignee: Aridis Pharmaceuticals
    Inventors: Vu Truong-Le, Satoshi Ohtake, Russell Andrew Martin, Binh V. Pham, Luisa Yee