Patents by Inventor Tohru Okabe

Tohru Okabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240164151
    Abstract: Provided is the following: a resin substrate layer; a thin-film transistor layer provided on the resin substrate layer, and having a stack of, in sequence, a gate insulating film, an interlayer insulating film, and a flattening film; and a light-emitting element layer provided on the thin-film transistor layer, with a plurality of first electrodes, a common edge cover that is common, a plurality of light-emitting function layers, and a second electrode that is common being stacked sequentially in correspondence with a plurality of subpixels constituting a display region. A non-display region that is in the form of an island within the display region has a through-hole. The non-display region includes a first light-blocking film provided on the periphery of the flattening film so as to cover the side wall of the periphery.
    Type: Application
    Filed: March 31, 2021
    Publication date: May 16, 2024
    Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
  • Publication number: 20240147789
    Abstract: A display device, includes: a base substrate layer; a thin-film transistor layer provided on the base substrate layer, and including a plurality of subpixels forming a display region, each of the subpixels being provided with a thin-film transistor on which a planarization film is stacked; and a light-emitting element layer provided on the thin-film transistor layer, and including a plurality of first electrodes, a common edge cover, a plurality of light-emitting functional layers, and a common second electrode, all of which are sequentially stacked on top of another in association with the plurality of subpixels, wherein each of the first electrodes has a peripheral edge portion provided to: surround, in plan view, the thin-film transistor corresponding to the first electrode; and protrude toward the base substrate layer.
    Type: Application
    Filed: April 27, 2021
    Publication date: May 2, 2024
    Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
  • Patent number: 11968861
    Abstract: An organic EL display (1) has a bend (B) where a slit (81) is bored in a base coat film (23), gate insulating film (27), first interlayer insulating film (31) and second interlayer insulating film (35). The bend is provided with a filler layer (83) filling the slit and covering both edges of the slit. The filler layer has a protrusion (85) overlapping each edge in the width direction of the slit. A routed wire (7) routed from the display region (D) and then routed over the filler layer to reach a terminal section (T) extends over the protrusion.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: April 23, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Ichikawa, Shinsuke Saida, Ryosuke Gunji, Hiroki Taniyama, Tohru Okabe, Akira Inoue, Hiroharu Jinmura, Yoshihiro Nakada, Koji Tanimura
  • Patent number: 11957015
    Abstract: A lead wiring line is provided in a frame region to extend therein while intersecting with a frame-shaped dam wall, is formed of a same material and in a same layer as each of a plurality of display wiring lines in which a first metal layer, a second metal layer, and a third metal layer are layered in sequence, is electrically connected to the plurality of display wiring lines on a display region side, and is electrically connected to a terminal on a terminal portion side. The third metal layer is provided to cover a side surface of the first metal layer, and a side surface and an upper face of the second metal layer.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 9, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Takeshi Yaneda
  • Patent number: 11957014
    Abstract: A display device includes: a plurality of control lines; a plurality of power supply lines; a plurality of data signal lines; an oxide semiconductor layer; a first metal layer; a gate insulation film; a first inorganic insulation film; a second metal layer; a second inorganic insulation film; and a third metal layer. The oxide semiconductor layer, in a plan view, contains therein semiconductor lines formed as isolated regions between a plurality of drivers and a display area. The semiconductor lines cross the plurality of control lines and the plurality of power supply lines, are in contact with the plurality of control lines via an opening in a gate insulation film, are in contact with the plurality of power supply lines via an opening in the first inorganic insulation film, and have a plurality of narrowed portions, such that thicker and thinner regions exist along the same line.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 9, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Hiroharu Jinmura, Akira Inoue
  • Patent number: 11950462
    Abstract: A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 2, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Akira Inoue, Hiroharu Jinmura, Takeshi Yaneda
  • Patent number: 11925078
    Abstract: A display device includes the following: a resin substrate; a TFT layer disposed on the resin substrate, the TFT layer having a stack of, in sequence, a base coat film, a semiconductor film, a gate insulating film, a first metal film, an interlayer insulating film, a second metal film, and a flattening film; a light-emitting element disposed on the TFT layer and forming a display region; and a plurality of TFTs disposed in the TFT layer in the display region. The base coat film includes an amorphous silicon film disposed at least all over the display region.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: March 5, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tokuo Yoshida, Tohru Okabe
  • Patent number: 11908873
    Abstract: An active matrix substrate including a resin substrate including a plurality of external connection terminals arranged near a display region, the active matrix substrate includes: a plurality of first lead wires each extending from one of the external connection terminals to the display region; and a plurality of second lead wires each extending from one of the external connection terminals to a separation line, the second lead wires being arranged with an arrangement pitch along the separation line, and the arrangement pitch of the second lead wires being greater than an arrangement pitch of the first lead wires.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Shinji Ichikawa, Shinsuke Saida, Shoji Okazaki, Tokuo Yoshida, Hiroki Taniyama, Kohji Ariga, Hiroharu Jinmura, Akira Inoue, Yoshihiro Nakada, Yoshihiro Kohara, Koji Tanimura
  • Patent number: 11889729
    Abstract: A display device includes a short ring TFT, wherein the short ring TFT includes a semiconductor layer, a first gate electrode, a second gate electrode, a first gate insulating film provided between the semiconductor layer and the first gate electrode, and a second gate insulating film provided between the semiconductor layer and the second gate electrode, one of a pair of adjacent lead-out wiring lines is electrically connected to a source region of the semiconductor layer, the other of the pair of adjacent lead-out wiring lines is electrically connected to a drain region of the semiconductor layer, one of the first gate electrode and the second gate electrode is electrically connected to the source region or the drain region, and the other of the first gate electrode and the second gate electrode is electrically connected to a threshold value control wiring line.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 30, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Takeshi Yaneda
  • Patent number: 11889728
    Abstract: A display device includes: a resin substrate; a TFT layer; and a light-emitting element. A bending portion is provided with a first resin film formed of the same material and in the same layer as those of a first flattening film, and the first resin film fills a slit. An upper face of the first resin film is provided with a plurality of first connection wiring lines formed of a third metal film, and the plurality of first connection wiring lines extend in parallel to each other in a direction intersecting the extending direction of the bending portion. The plurality of first connection wiring lines are electrically connected to a plurality of first lead-out wiring lines, respectively in a display region side of the slit, and electrically connected to a plurality of second lead-out wiring lines, respectively in a terminal portion side of the slit.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 30, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Shinji Ichikawa, Shinsuke Saida, Shoji Okazaki, Tokuo Yoshida, Hiroki Taniyama, Kohji Ariga, Hiroharu Jinmura, Akira Inoue, Yoshihiro Nakada, Yoshihiro Kohara, Koji Tanimura
  • Publication number: 20240023384
    Abstract: A first planarization film is provided to opposing sides out of a folding portion to: fill widthwise opposing end portions of a slit; and expose a surface of a resin substrate layer in an intermediate position between the widthwise opposing end portions. In the folding portion and at the opposing sides out of the folding portion, a plurality of routed wires are provided on the first planarization film and the resin substrate layer, and extending in parallel with one another in a direction perpendicular to a direction in which the folding portion extends. The plurality of routed wires are each electrically connected to a corresponding one of a plurality of display wires toward a display region and to a corresponding one of a plurality of terminals toward a terminal unit. The plurality of routed wires are formed of a same material as, and in a same layer as, a wiring layer is.
    Type: Application
    Filed: November 30, 2020
    Publication date: January 18, 2024
    Inventors: TOHRU OKABE, SHOJI OKAZAKI, SHINSUKE SAIDA, SHINJI ICHIKAWA, HIROKI TANIYAMA
  • Patent number: 11800738
    Abstract: The disclosure has an object to achieve a high level of height precision for spacers on a back plane. A display device includes: edge covers having a plurality of openings in which first electrodes are exposed; and a planarization film having first flat portions, second flat portions, and contact holes. The plurality of openings respectively overlap the first flat portions in a plan view. The second flat portions are located between the plurality of openings in a plan view. Each edge cover overlapping one of the first flat portions in a plan view has, on a second electrode side, a surface that has a first height from a bottom surface of the planarization film on a substrate side. Each second flat portion has, on the second electrode side, a surface that has a second height from the bottom surface. The first height is smaller than the second height.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: October 24, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Hiroki Taniyama, Shinji Ichikawa, Ryosuke Gunji, Yoshihiro Nakada, Akira Inoue, Hiroharu Jinmura
  • Patent number: 11800755
    Abstract: In the display device according to the disclosure, a first bank includes a first bank lower portion in the same layer as a flattening film and a first bank upper portion in the same layer as an edge cover. A second bank includes a second bank lower portion in the same layer as the flattening film and a second bank upper portion in the same layer as the edge cover. The first bank upper portion covers an upper surface and a side surface of the first bank lower portion, the side surface being on a side close to a display region. An inclination angle of a side surface of the first bank upper portion on a side close to the display region is larger than an inclination angle of the side surface of the first bank lower portion on the side close to the display region.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 24, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinsuke Saida, Tohru Okabe, Shinji Ichikawa, Ryosuke Gunji, Hiroki Taniyama, Hiroharu Jinmura, Akira Inoue, Yoshihiro Nakada
  • Publication number: 20230337484
    Abstract: A display device includes a display region of an image, a terminal region provided with a plurality of terminals, a bending region being a region between the display region and the terminal region and being bendable, the bending region includes a first resin layer, a plurality of relay wiring lines provided on the first resin layer and provided between the display region and the terminal region, a second resin layer provided at an upper layer of the plurality of relay wiring lines and the first resin layer, and a third resin layer provided on the second resin layer, and a surface of each of the second resin layer and the third resin layer is provided with a plurality of anchor portions each of which includes a protruding portion provided at one surface and a recessed portion provided at the other surface, the recessed portion being engaged with the protruding portion.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 19, 2023
    Inventors: TOHRU OKABE, SHOJI OKAZAKI, SHINSUKE SAIDA, SHINJI ICHIKAWA
  • Publication number: 20230337486
    Abstract: A display device includes: a resin substrate layer; a thin film transistor layer on the resin substrate layer, the thin film transistor layer including a sequential stack of an inorganic insulating film, a wiring layer, and a planarization film; and a light-emitting element layer, wherein a frame area is provided, a terminal section is provided, a bending section is provided between the display area and the terminal section, a plurality of routing wires are provided in the bending section and two sides of the bending section, and at least one of the plurality of routing wires includes: a display-side wiring section on an edge portion of the inorganic insulating film; a terminal-side wiring section on another edge portion of the inorganic insulating film; and an intermediate wiring section electrically connected to the display-side wiring section and the terminal-side wiring section respectively.
    Type: Application
    Filed: September 28, 2020
    Publication date: October 19, 2023
    Inventors: TOHRU OKABE, SHOJI OKAZAKI, SHINSUKE SAIDA, SHINJI ICHIKAWA, HIROKI TANIYAMA
  • Patent number: 11793041
    Abstract: In a TFT layer provided on a base substrate, a first metal film, a first inorganic insulating film, a second metal film, a second inorganic insulating film, a third metal film, a first flattening film, a fourth metal film, and a second flattening film are sequentially layered. In a frame region, a slit is formed in the second flattening film to surround a display region, a first conductive layer formed by the fourth metal film is provided on the first flattening film exposed from the slit, and a TFT of a drive circuit is provided on the base substrate side of the first conductive layer to overlap with the first conductive layer.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 17, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Kohji Ariga, Hiroki Taniyama, Shinji Ichikawa, Shinsuke Saida, Hiroharu Jinmura, Akira Inoue, Yoshihiro Kohara, Koji Tanimura, Yoshihiro Nakada
  • Publication number: 20230309362
    Abstract: A display device, includes: a resin substrate layer; a thin-film transistor layer; a light-emitting-element layer provided on the thin-film transistor layer and including a plurality of first electrodes, a plurality of light-emitting functional layers, and a second electrode stacked on top of another in a stated order; a frame region; a terminal unit; a folding portion; a slit; a filling resin film; a plurality of routed wires; and a reinforcing resin film, wherein the reinforcing resin film is provided with a first dam wall toward the display region, the first dam wall being in contact with the reinforcing resin film and extending in the direction in which the folding portion extends, and the reinforcing resin film is provided with a second dam wall toward the terminal unit, the second dam wall being in contact with the reinforcing resin film and extending in the direction in which the folding portion extends.
    Type: Application
    Filed: June 25, 2020
    Publication date: September 28, 2023
    Inventors: TOHRU OKABE, SHOJI OKAZAKI, SHINJI ICHIKAWA, HIROKI TANIYAMA, SHINSUKE SAIDA
  • Publication number: 20230292561
    Abstract: A display device includes a display region of an image, a terminal region provided with a plurality of terminals, and a bending region being a region between the display region and the terminal region and being bendable, the bending region includes a first resin layer, a plurality of relay wiring lines provided on the first resin layer and provided between the display region and the terminal region, and a second resin layer provided on the first resin layer and covering the plurality of relay wiring lines, and the first resin layer and the second resin layer in the bending region are provided with a plurality of slits having a depth from a surface of the second resin layer to the first resin layer at outer sides than the relay wiring lines provided at both ends among the plurality of relay wiring lines in a plan view.
    Type: Application
    Filed: July 1, 2020
    Publication date: September 14, 2023
    Inventors: TOHRU OKABE, SHOJI OKAZAKI, SHINSUKE SAIDA, SHINJI ICHIKAWA
  • Publication number: 20230255076
    Abstract: A thin-film transistor layer includes: a first wiring layer; a first planarization film; a second wiring layer; and a second planarization film, all of which are stacked on top of another in a stated order. The first planarization film and the second planarization film include a first slit shaped into a frame, provided between the display region and the first dam wall, and penetrating the first planarization film and the second planarization film. In the first slit, a first frame wire and a second frame wire have respective edge portions facing each other and covered with a protective film made of an inorganic insulating film included in the thin-film transistor layer.
    Type: Application
    Filed: July 20, 2020
    Publication date: August 10, 2023
    Inventors: TOHRU OKABE, SHOJI OKAZAKI, SHINSUKE SAIDA, SHINJI ICHIKAWA
  • Publication number: 20230217786
    Abstract: A display device includes a display panel, wherein the display panel has a display area and a non-display area along a periphery of the display area, the non-display area includes a frame area and also includes an intermediate area between the display area and the frame area, and letting a first areal ratio be an areal fraction of lateral cross-sectional areas of a plurality of spacers per unit area in the display area, a second areal ratio be an areal fraction of lateral cross-sectional areas of the plurality of spacers per unit area in the intermediate area, and a third areal ratio be an areal fraction of lateral cross-sectional areas of the plurality of spacers per unit area in the frame area, the plurality of spacers are arranged so as to satisfy relations, first areal ratio < second areal ratio < third areal ratio.
    Type: Application
    Filed: May 28, 2020
    Publication date: July 6, 2023
    Applicants: SHARP KABUSHIKI KAISHA, SHARP KABUSHIKI KAISHA
    Inventors: TOHRU OKABE, SHOJI OKAZAKI, SHINSUKE SAIDA, SHINJI ICHIKAWA