Patents by Inventor Tomoaki Atsumi
Tomoaki Atsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10910404Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.Type: GrantFiled: January 24, 2019Date of Patent: February 2, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshinori Ieda, Atsuo Isobe, Yutaka Shionoiri, Tomoaki Atsumi
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Publication number: 20210012816Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.Type: ApplicationFiled: November 30, 2018Publication date: January 14, 2021Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tomoaki ATSUMI, Kiyoshi KATO, Tatsuya ONUKI, Shunpei YAMAZAKI
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Publication number: 20200373302Abstract: A novel semiconductor device is provided. A back gate voltage of a transistor including a gate and a back gate is adjusted based on the operating temperature. The operating temperature is acquired by a temperature detector circuit. The temperature detection circuit outputs the temperature information as a digital signal. The digital signal is input to a voltage control circuit. The voltage control circuit outputs a first voltage corresponding to the digital signal. The back gate voltage is determined by a voltage in which a first voltage is added to a reference voltage.Type: ApplicationFiled: November 30, 2018Publication date: November 26, 2020Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tatsuya ONUKI, Takanori MATSUZAKI, Tomoaki ATSUMI, Takahiko ISHIZU
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Publication number: 20200365591Abstract: A semiconductor device capable of obtaining the threshold voltage of a transistor is provided. The semiconductor device includes a first transistor, a first capacitor, a first output terminal, a first switch, and a second switch. A gate and a source of the first transistor are electrically connected to each other. A first terminal of the first capacitor is electrically connected to the source. A second terminal and the first output terminal of the first capacitor are electrically connected to a back gate of the first transistor. The first switch controls input of a first voltage to the back gate. A second voltage is input to a drain of the first transistor. The second switch controls input of a third voltage to the source.Type: ApplicationFiled: January 11, 2019Publication date: November 19, 2020Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hitoshi KUNITAKE, Ryunosuke HONDA, Tomoaki ATSUMI
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Publication number: 20200343251Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j?1th sub memory cell.Type: ApplicationFiled: March 6, 2020Publication date: October 29, 2020Inventors: Tomoaki ATSUMI, Shuhei NAGATSUKA, Tamae MORIWAKA, Yuta ENDO
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Publication number: 20200342928Abstract: A novel storage device and a novel semiconductor device are provided. In the storage device, a cell array including a plurality of memory cells is stacked above a control circuit, and the cell array operates separately in a plurality of blocks. Furthermore, a plurality of electrodes are included between the control circuit and the cell array. The electrode is provided for a corresponding block to overlap with the block, and a potential of the electrode can be changed for each block. The electrode has a function of aback gate of a transistor included in the memory cell, and a potential of the electrode is changed for each block, whereby the electrical characteristics of the transistor included in the memory cell can be changed. Moreover, the electrode can reduce noise caused in the control circuit.Type: ApplicationFiled: January 14, 2020Publication date: October 29, 2020Inventors: Shunpei YAMAZAKI, Kiyoshi KATO, Tomoaki ATSUMI, Shuhei NAGATSUKA, Hitoshi KUNITAKE
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Publication number: 20200336066Abstract: Provided is a structure which is capable of central control of an electric device and a sensor device and a structure which can reduce power consumption of an electric device and a sensor device. A central control system includes at least a central control device, an output unit, and an electric device or a sensor device. The central control device performs arithmetic processing on information transmitted from the electric device or the sensor device and makes the output unit output information obtained by the arithmetic processing. It is possible to know the state of the electric device or the sensor device even apart from the electric device or the sensor device. The electric device or the sensor device includes a transistor which includes an activation layer using a semiconductor with the band gap wider than that of single crystal silicon.Type: ApplicationFiled: April 15, 2020Publication date: October 22, 2020Inventors: Shunpei YAMAZAKI, Tatsuji NISHIJIMA, Hidetomo KOBAYASHI, Tomoaki ATSUMI, Kiyoshi KATO
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Publication number: 20200265887Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.Type: ApplicationFiled: November 12, 2018Publication date: August 20, 2020Inventors: Tomoaki ATSUMI, Kiyoshi KATO, Shuhei MAEDA
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Publication number: 20200211627Abstract: The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.Type: ApplicationFiled: January 2, 2020Publication date: July 2, 2020Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Junpei Sugao
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Patent number: 10693448Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.Type: GrantFiled: March 25, 2019Date of Patent: June 23, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Yutaka Shionoiri, Tomoaki Atsumi, Takanori Matsuzaki
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Patent number: 10630176Abstract: Provided is a structure which is capable of central control of an electric device and a sensor device and a structure which can reduce power consumption of an electric device and a sensor device. A central control system includes at least a central control device, an output unit, and an electric device or a sensor device. The central control device performs arithmetic processing on information transmitted from the electric device or the sensor device and makes the output unit output information obtained by the arithmetic processing. It is possible to know the state of the electric device or the sensor device even apart from the electric device or the sensor device. The electric device or the sensor device includes a transistor which includes an activation layer using a semiconductor with the band gap wider than that of single crystal silicon.Type: GrantFiled: November 8, 2017Date of Patent: April 21, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tatsuji Nishijima, Hidetomo Kobayashi, Tomoaki Atsumi, Kiyoshi Kato
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Patent number: 10593683Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-1th sub memory cell.Type: GrantFiled: February 14, 2019Date of Patent: March 17, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Shuhei Nagatsuka, Tamae Moriwaka, Yuta Endo
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Patent number: 10529413Abstract: The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.Type: GrantFiled: August 14, 2018Date of Patent: January 7, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Junpei Sugao
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Patent number: 10522688Abstract: A semiconductor device capable of holding data for a long time is provided. The semiconductor device includes a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. A first terminal of the second transistor is electrically connected to a gate of the second transistor and the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor has a wider bandgap than the first semiconductor.Type: GrantFiled: December 15, 2016Date of Patent: December 31, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Tomoaki Atsumi, Shunpei Yamazaki, Haruyuki Baba, Shinpei Matsuda
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Patent number: 10500908Abstract: To provide a circuit with low power consumption, a semiconductor device with low power consumption, a highly reliable semiconductor device, a tire whose performance is controlled, a moving object whose performance is controlled, or a moving object with a high degree of safety. A tire provided with a semiconductor device is provided. The semiconductor device includes a circuit portion, an antenna, and a sensor element. The circuit portion includes a transistor. The transistor includes an oxide semiconductor. The sensor element is configured to measure the air pressure of the tire.Type: GrantFiled: July 10, 2018Date of Patent: December 10, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Masayuki Sakakura, Kazuaki Ohshima
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Patent number: 10388670Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.Type: GrantFiled: March 2, 2017Date of Patent: August 20, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshinori Ieda, Atsuo Isobe, Yutaka Shionoiri, Tomoaki Atsumi
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Publication number: 20190222209Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Inventors: Kiyoshi KATO, Yutaka SHIONOIRI, Tomoaki ATSUMI, Takanori MATSUZAKI
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Publication number: 20190189622Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-1th sub memory cell. [Selected Drawing] FIG.Type: ApplicationFiled: February 14, 2019Publication date: June 20, 2019Inventors: Tomoaki ATSUMI, Shuhei NAGATSUKA, Tamae MORIWAKA, Yuta ENDO
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Patent number: 10324521Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.Type: GrantFiled: October 21, 2016Date of Patent: June 18, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsuji Nishijima, Hidetomo Kobayashi, Tomoaki Atsumi, Kiyoshi Kato, Shunpei Yamazaki
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Publication number: 20190157309Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.Type: ApplicationFiled: January 24, 2019Publication date: May 23, 2019Inventors: Yoshinori IEDA, Atsuo ISOBE, Yutaka SHIONOIRI, Tomoaki ATSUMI