Patents by Inventor Tomohiko Mori

Tomohiko Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10283626
    Abstract: A semiconductor device may include a nitride semiconductor layer, an insulation gate section, and a heterojunction region, wherein the nitride semiconductor layer may include an n-type vertical drift region, a p-type channel region adjoining the vertical drift region, and an n-type source region separated from the vertical drift region by the channel region, wherein the insulation gate section is opposed to a portion of the channel region that separates the vertical drift region and the source region, the heterojunction region is in contact with at least a part of a portion of the vertical drift region that is disposed at the one of main surfaces, and the heterojunction region is an n-type nitride semiconductor or an i-type nitride semiconductor having a bandgap wider than a bandgap of the vertical drift region.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 7, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidemoto Tomita, Masakazu Kanechika, Hiroyuki Ueda, Tomohiko Mori
  • Patent number: 10276707
    Abstract: A switching element includes a semiconductor substrate that includes a first n-type semiconductor layer, a p-type body layer constituted by an epitaxial layer, and a second n-type semiconductor layer separated from the first n-type semiconductor layer by the body layer, a gate insulating film that covers a range across the surface of the first n-type semiconductor layer, the surface of the body layer, and the surface of the second n-type semiconductor layer, and a gate electrode that faces the body layer through the gate insulating film. An interface between the first n-type semiconductor layer and the body layer includes an inclined surface. The inclined surface is inclined such that the depth of the body layer increases as a distance from an end of the body layer increases in a horizontal direction. The inclined surface is disposed below the gate electrode.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: April 30, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tetsuya Yamada, Takashi Okawa, Tomohiko Mori, Hiroyuki Ueda
  • Publication number: 20190109224
    Abstract: A nitride semiconductor apparatus includes a nitride semiconductor layer, a gate insulating film, a source electrode, a drain electrode, and a gate electrode. The nitride semiconductor layer includes a first body layer, a second body layer, a drift layer, a first source layer, and a second source layer. The drift layer includes a first drift layer that extends from a position in contact with a bottom surface of the first body layer to a position in contact with a bottom surface of the second body layer, and an electric field relaxation layer that is in contact with a lower end portion of a side surface of the first body layer and a lower end portion of a side surface of the second body layer, is in contact with the first drift layer, and has a second conduction type impurity concentration lower than that of the first drift layer.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 11, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidemoto Tomita, Hiroyuki Ueda, Tomohiko Mori
  • Patent number: 10256295
    Abstract: A semiconductor device includes an outside-of-well n-type region, a p-type well region surrounded by the outside-of-well n-type region, an inside-of-well n-type region, and a gate electrode. The outside-of-well n-type region includes an impurity low-concentration region that is in contact with the p-type well region, and an impurity high-concentration region that is separated from the p-type well region by the impurity low-concentration region.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 9, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masahiro Kawakami, Tomohiko Mori, Hiroyuki Ueda
  • Patent number: 10242869
    Abstract: A method of manufacturing a switching element includes forming a recessed portion in a surface of a GaN semiconductor substrate in which a first n-type semiconductor layer is exposed on the surface, growing a p-type body layer within the recessed portion and on the surface of the GaN semiconductor substrate, removing a surface layer portion of the body layer to expose the first n-type semiconductor layer on the surface of the GaN semiconductor substrate, and leave the body layer within the recessed portion, forming a second n-type semiconductor layer which is separated from the first n-type semiconductor layer by the body layer and is exposed on the surface of the GaN semiconductor substrate, and forming a gate electrode which faces the body layer through an insulating film.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: March 26, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tetsuya Yamada, Hiroyuki Ueda, Tomohiko Mori
  • Publication number: 20180322999
    Abstract: An electronic component includes a main body composed of an insulator, a coating film covering the main body, a circuit element located inside the main body, and outer electrodes. The insulator contains a metal magnetic powder. The coating film is composed of a resin and a cationic element contained in the insulator.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hironobu KUBOTA, Mitsunori INOUE, Tomohiko MORI, Gota SHINOHARA, Kenji NISHIYAMA
  • Publication number: 20180323000
    Abstract: An electronic component includes a main body composed of an insulator, a coating film covering the main body, a circuit element located inside the main body, and outer electrodes. The insulator contains a metal magnetic powder. The coating film is composed of a resin and a cationic element contained in the insulator.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hironobu KUBOTA, Mitsunori INOUE, Tomohiko MORI, Gota SHINOHARA, Kenji NISHIYAMA
  • Publication number: 20180240584
    Abstract: A method of manufacturing a ceramic electronic component such that Voids of the ceramic element and voids at the interfaces between the ceramic element and the external electrodes are filled with a resin composition by applying, to the ceramic electronic component, a resin-containing solution that has the function of etching the surface of the ceramic element to ionize constituent elements of the ceramic element. The resin composition includes a resin, and cationic elements among the constituent elements of the ceramic elements, which are ionized and deposited from the ceramic element.
    Type: Application
    Filed: April 24, 2018
    Publication date: August 23, 2018
    Inventors: Mitsunori Inoue, Tomohiko Mori
  • Publication number: 20180233591
    Abstract: A semiconductor device includes a semiconductor substrate, a source electrode, a drain electrode, and a gate electrode disposed on the semiconductor substrate via a gate insulator film. The semiconductor substrate includes a first portion constituted of GaN and a second portion constituted of AlxGa(1-x)N (0<x?1). The first portion includes an n-type source region being in contact with the source electrode, an n-type drain region being in contact with the drain electrode, a p-type body region intervening between the source region and the drain region and being in contact with the source electrode, and an n-type drift region intervening between the body region and the drain region and having a carrier density that is lower than a carrier density of the drain region. The second portion includes a barrier region being in contact with each of the source electrode, the body region and the drift region.
    Type: Application
    Filed: December 27, 2017
    Publication date: August 16, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Atsushi WATANABE, Hiroyuki UEDA, Tomohiko MORI
  • Publication number: 20180182883
    Abstract: A switching element includes a semiconductor substrate that includes a first n-type semiconductor layer, a p-type body layer constituted by an epitaxial layer, and a second n-type semiconductor layer separated from the first n-type semiconductor layer by the body layer, a gate insulating film that covers a range across the surface of the first n-type semiconductor layer, the surface of the body layer, and the surface of the second n-type semiconductor layer, and a gate electrode that faces the body layer through the gate insulating film. An interface between the first n-type semiconductor layer and the body layer includes an inclined surface. The inclined surface is inclined such that the depth of the body layer increases as a distance from an end of the body layer increases in a horizontal direction. The inclined surface is disposed below the gate electrode.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 28, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tetsuya YAMADA, Takashi OKAWA, Tomohiko MORI, Hiroyuki UEDA
  • Publication number: 20180182621
    Abstract: A method of manufacturing a switching element includes forming a recessed portion in a surface of a GaN semiconductor substrate in which a first n-type semiconductor layer is exposed on the surface, growing a p-type body layer within the recessed portion and on the surface of the GaN semiconductor substrate, removing a surface layer portion of the body layer to expose the first n-type semiconductor layer on the surface of the GaN semiconductor substrate, and leave the body layer within the recessed portion, forming a second n-type semiconductor layer which is separated from the first n-type semiconductor layer by the body layer and is exposed on the surface of the GaN semiconductor substrate, and forming a gate electrode which faces the body layer through an insulating film.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 28, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tetsuya YAMADA, Hiroyuki UEDA, Tomohiko MORI
  • Patent number: 9997293
    Abstract: A ceramic electronic component that includes a ceramic main body, a coating film and external electrodes on the surface of the ceramic main body. The coating film is selectively formed on the surface of the ceramic main body by applying, to the surface of the ceramic main body, a resin-containing solution that etches the surface of the ceramic main body so as to ionize constituent elements of the ceramic main body. The coating film includes a resin and the constituent elements of the ceramic main body, which were ionized and deposited from the ceramic main body.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 12, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Mitsunori Inoue, Tomohiko Mori
  • Publication number: 20180122311
    Abstract: A display control device of the present invention include a correction circuit (11) that obtains integrated values by integrating, for a period of 0.5 frame or longer, each of the values of voltages corresponding to input levels of gray that are applied to two display pixels on the same gate lines, obtains voltage values by adding the difference between the integrated values to each of the values of the voltages corresponding to the input levels of gray, and uses the voltage values as output levels of gray of the current frame that are given to the two display pixels. This prevents the appearance of transcriptions in displaying 1-dot horizontal stripes during double-source driving.
    Type: Application
    Filed: April 14, 2016
    Publication date: May 3, 2018
    Inventors: Tomohiko MORI, Kazunari TOMIZAWA
  • Patent number: 9959975
    Abstract: A ceramic electronic component that includes a ceramic element, and a coating film and external electrodes on a surface of the ceramic element. The coating film includes cationic elements from a constituent element of the ceramic element, which are ionized and deposited from the ceramic element, and a resin. The surface of the coating film is recessed relative to a surface of wrapping parts of the external electrodes on the surface of the ceramic element.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: May 1, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Mitsunori Inoue, Yoshihito Okutomi, Tomohiko Mori
  • Publication number: 20180102405
    Abstract: A semiconductor device includes an outside-of-well n-type region, a p-type well region surrounded by the outside-of-well n-type region, an inside-of-well n-type region, and a gate electrode. The outside-of-well n-type region includes an impurity low-concentration region that is in contact with the p-type well region, and an impurity high-concentration region that is separated from the p-type well region by the impurity low-concentration region.
    Type: Application
    Filed: September 14, 2017
    Publication date: April 12, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masahiro KAWAKAMI, Tomohiko MORI, Hiroyuki UEDA
  • Publication number: 20180090600
    Abstract: A semiconductor device may include a nitride semiconductor layer, an insulation gate section, and a heterojunction region, wherein the nitride semiconductor layer may include an n-type vertical drift region, a p-type channel region adjoining the vertical drift region, and an n-type source region separated from the vertical drift region by the channel region, wherein the insulation gate section is opposed to a portion of the channel region that separates the vertical drift region and the source region, the heterojunction region is in contact with at least a part of a portion of the vertical drift region that is disposed at the one of main surfaces, and the heterojunction region is an n-type nitride semiconductor or an i-type nitride semiconductor having a bandgap wider than a bandgap of the vertical drift region.
    Type: Application
    Filed: August 8, 2017
    Publication date: March 29, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidemoto TOMITA, Masakazu KANECHIKA, Hiroyuki UEDA, Tomohiko MORI
  • Patent number: 9886932
    Abstract: A multi-primary color display device (100) includes: a multi-primary color display panel (10) including a pixel that is defined by a plurality of sub pixels including a red sub pixel (R), a green sub pixel (G), a blue sub pixel (B), and a yellow sub pixel (Ye); and a signal converting circuit (20) converting a three-primary color image signal corresponding to three primary colors into a multi-primary color image signal corresponding to four or more primary colors. The signal converting circuit (20), in a case where a three-primary color image signal representing at least an achromatic color of a half tone is input, performs a signal conversion such that variations in luminance levels of the plurality of sub pixels are equalized.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: February 6, 2018
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuichi Yoshida, Kazunari Tomizawa, Tomohiko Mori, Makoto Hasegawa
  • Patent number: 9704428
    Abstract: A display device is disclosed, along with a display method capable of displaying an input image having a resolution higher than the resolution of a display panel without degradation in display quality. The display device is a display device for displaying an image with each frame divided into two sub-frames. In the display device, a bright sub-pixel and a dark sub-pixel in each pixel are interchanged every sub-frame, and an input signal has a vertical resolution twice that of a display panel. The display device displays an image corresponding to the input signal by making the sub-frames different from each other in a voltage supplied to each pixel.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: July 11, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomohiko Mori, Kazunari Tomizawa, Makoto Hasegawa, Yuichi Yoshida
  • Publication number: 20170192307
    Abstract: A liquid crystal display device according to the present invention has a display area that includes a plurality of pixels (Px). The display area is made up of n kinds of domains (where n is an integer that is equal to or greater than two and equal to or smaller than four). The directors of the n kinds of domains define mutually different alignment directions. If the domain structure of each pixel (Px) is defined by the kinds of the domains that form the pixel (Px), the number k of the kinds of the domains that form the pixel (Px), and the arrangement of the domains in the pixel (Px), the display area includes a pixel, of which k is less than n and of which the domain structure is different from the domain structures of adjacent pixels.
    Type: Application
    Filed: March 22, 2017
    Publication date: July 6, 2017
    Inventors: Isamu MIYAKE, Tomohiko MORI, Iichiroh INOUE
  • Patent number: 9638960
    Abstract: A liquid crystal display device according to the present invention has a display area that includes a plurality of pixels (Px). The display area is made up of n kinds of domains (where n is an integer that is equal to or greater than two and equal to or smaller than four). The directors of the n kinds of domains define mutually different alignment directions. If the domain structure of each pixel (Px) is defined by the kinds of the domains that form the pixel (Px), the number k of the kinds of the domains that form the pixel (Px), and the arrangement of the domains in the pixel (Px), the display area includes a pixel, of which k is less than n and of which the domain structure is different from the domain structures of adjacent pixels.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 2, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Isamu Miyake, Tomohiko Mori, Iichiroh Inoue