Patents by Inventor Tomohiro Kawakubo
Tomohiro Kawakubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20100172200Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: November 4, 2009Publication date: July 8, 2010Applicant: FUJITSU LIMITEDInventors: Tomohiro KAWAKUBO, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
-
Publication number: 20100146201Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: November 4, 2009Publication date: June 10, 2010Applicant: FUJITSU LIMITEDInventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
-
Patent number: 7688661Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: GrantFiled: September 22, 2008Date of Patent: March 30, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
-
Patent number: 7633825Abstract: A semiconductor memory device includes a DRAM memory core circuit including a word line, a power supply circuit configured to operate in a selected one of a first state and a second state to generate a predetermined power supply voltage for provision to the DRAM memory core circuit, the power supply circuit consuming a larger electric current in the first state than in the second state, and a control circuit configured to control the power supply circuit such that the power supply circuit is shifted from the first state to the second state, and is then brought back to the first state during a period from activation of the word line to deactivation of the word line.Type: GrantFiled: May 15, 2007Date of Patent: December 15, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Yoshiaki Okuyama, Atsushi Takeuchi, Tomohiro Kawakubo
-
Publication number: 20090190418Abstract: A semiconductor memory comprising an address transition detection circuit for detecting a transition of an address and outputs an address detection signal; an address input circuit for inputting an input address based upon the address detection signal; a command judgment circuit for decoding a command signal input and outputting a command judgment signal; a redundancy circuit for making a redundancy judgment based upon a redundancy judgment signal indicating timing of a redundancy judgment, wherein the redundancy circuit includes a redundancy judgment speed-up circuit for controlling an output of the redundancy judgment signal based upon a predetermined command signal.Type: ApplicationFiled: September 11, 2008Publication date: July 30, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Toshikazu NAKAMURA, Tomohiro KAWAKUBO
-
Patent number: 7552369Abstract: A semiconductor device includes a memory cell array, in which bit lines intersect word lines to form a memory cell. Representative pads are selected from among pads. Data input to the representative pads is decompressed to data corresponding to all of the pads, and is written in corresponding memory cells. The data is read and divided into number of groups corresponding to number of the representative pads. It is determined whether the data in each group coincide with the data input to the representative pads. Output to the representative pads is controlled based on a result of the determination.Type: GrantFiled: March 30, 2005Date of Patent: June 23, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Tomohiro Kawakubo
-
Publication number: 20090089493Abstract: Operation control circuits start a first operation of any of memory cores in response to a first operation command, start a second operation of any of the memory cores in response to a second operation command, and terminate the first operation and continue the second operation in response to a termination command to terminate operations of the plurality of memory cores. For example, the semiconductor memory is mounted on a system together with a controller accessing the semiconductor memory. The termination of the operation in response to the termination command is judged in accordance with an operation state of the memory core. Accordingly, it is possible to terminate the operation of the memory core requiring the termination of operation without specifying the memory core from outside.Type: ApplicationFiled: September 22, 2008Publication date: April 2, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hitoshi IKEDA, Takahiko Sato, Tomohiro Kawakubo
-
Patent number: 7495986Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: GrantFiled: July 27, 2005Date of Patent: February 24, 2009Assignee: Fujitsu Microelectronic LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
-
Patent number: 7483323Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: GrantFiled: September 6, 2006Date of Patent: January 27, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
-
Publication number: 20090016142Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: September 22, 2008Publication date: January 15, 2009Inventors: Shinya FUJIOKA, Tomohiro KAWAKUBO, Koichi NISHIMURA, Kotoku SATO
-
Publication number: 20090010080Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: August 29, 2008Publication date: January 8, 2009Inventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
-
Patent number: 7471587Abstract: A core control circuit outputs operation control signals to a memory core in order to perform refresh operations in response to an internal refresh request from a refresh request generating circuit and an external refresh request. The core control circuit sets the number of memory cells each subjected to the refresh operation in response to the external refresh request larger than the number of memory cells each subjected to the refresh operations in response to the internal refresh request. By relatively increasing the number of memory cells each subjected to the refresh operation in response to one external refresh request, the number of external refresh requests required to refresh all memory cells can be reduced. Accordingly, the frequency with which the external refresh request is supplied to the semiconductor memory can be lowered, which can improve access efficiency.Type: GrantFiled: May 2, 2007Date of Patent: December 30, 2008Assignee: Fujitsu LimitedInventor: Tomohiro Kawakubo
-
Publication number: 20080151670Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: February 23, 2007Publication date: June 26, 2008Inventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
-
Publication number: 20070268769Abstract: A semiconductor memory device includes a DRAM memory core circuit including a word line, a power supply circuit configured to operate in a selected one of a first state and a second state to generate a predetermined power supply voltage for provision to the DRAM memory core circuit, the power supply circuit consuming a larger electric current in the first state than in the second state, and a control circuit configured to control the power supply circuit such that the power supply circuit is shifted from the first state to the second state, and is then brought back to the first state during a period from activation of the word line to deactivation of the word line.Type: ApplicationFiled: May 15, 2007Publication date: November 22, 2007Inventors: Yoshiaki Okuyama, Atsushi Takeuchi, Tomohiro Kawakubo
-
Publication number: 20070268768Abstract: A core control circuit outputs operation control signals to a memory core in order to perform refresh operations in response to an internal refresh request from a refresh request generating circuit and an external refresh request. The core control circuit sets the number of memory cells each subjected to the refresh operation in response to the external refresh request larger than the number of memory cells each subjected to the refresh operations in response to the internal refresh request. By relatively increasing the number of memory cells each subjected to the refresh operation in response to one external refresh request, the number of external refresh requests required to refresh all memory cells can be reduced. Accordingly, the frequency with which the external refresh request is supplied to the semiconductor memory can be lowered, which can improve access efficiency.Type: ApplicationFiled: May 2, 2007Publication date: November 22, 2007Inventor: Tomohiro Kawakubo
-
Publication number: 20070014178Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: September 6, 2006Publication date: January 18, 2007Inventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
-
Publication number: 20070002664Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: September 6, 2006Publication date: January 4, 2007Inventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
-
Publication number: 20060092681Abstract: A semiconductor device includes a memory cell array, in which bit lines intersect word lines to form a memory cell. Representative pads are selected from among pads. Data input to the representative pads is decompressed to data corresponding to all of the pads, and is written in corresponding memory cells. The data is read and divided into number of groups corresponding to number of the representative pads. It is determined whether the data in each group coincide with the data input to the representative pads. Output to the representative pads is controlled based on a result of the determination.Type: ApplicationFiled: March 30, 2005Publication date: May 4, 2006Inventor: Tomohiro Kawakubo
-
Publication number: 20050262369Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: July 27, 2005Publication date: November 24, 2005Inventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
-
Patent number: 6845055Abstract: A semiconductor memory that can make the transition from a power-down state in a synchronous mode to an asynchronous mode without setting by a control register and that needs no extra circuits. A state selection section chooses, by selecting an existing internal signal the level of which changes in the power-down state or an existing internal signal the level of which does not change in the power-down state in accordance with a state selection signal inputted in advance and passing a signal selected to a synchronous/asynchronous mode setting section, whether the semiconductor memory should make the transition from the power-down state to a standby state in the synchronous mode or a standby state in the asynchronous mode. In accordance with the selection by the state selection section, the synchronous/asynchronous mode setting section generates a signal for causing the semiconductor memory to make the transition between the synchronous mode and the asynchronous mode.Type: GrantFiled: June 15, 2004Date of Patent: January 18, 2005Assignee: Fujitsu LimitedInventors: Toru Koga, Tomohiro Kawakubo, Tatsuya Kanda