Abstract: A CBR/VBR traffic scheduler includes multiple CBR/VBR shapers to shape traffic over a wide range of peak cell rates for multiple CBR and VBR connection. Each shaper points to one or more VCs in a link list and includes a PCR counter initialized to a first value, an SCR counter initialized to a second and an arbitration counter. Each shaper is also connected to one of several clock sources, each having an associated clock cycle. A priority encoder, coupled to each arbitration counter, provides for determining priority between shapers having one or more associated VCs ready for transmission. Both the PCR counter and the SCR counter for each shaper is decremented during each associated clock cycle. For each shaper, when the PCR counter is decremented to a value of zero, the arbitration counter is initialized to a preset value and enabled for selection by the priority encoder.

Abstract: This invention is an improved structure of a windshield wiper. This structure has a long main body of wiper with a pressure plate inside. On both long sides of the main body, there are trenches which are used to fix the main body on the wiper. On one side of the trench, there is an indented trough. Finally, at the bottom of the main body, there are at least two main rubber blades.

Abstract: This invention is about a windshield with pressurizing function. The wiper has a long wiper holder including a big frame, two medium-sized frames and 2 small frames, arranged in layers. Other parts include a scraping plate, installed at one side of the wiper holder. The features of this wiper are that it has four springs. Two springs are installed in between the two medium-sized frames and the scraping plate. The other two springs are installed in between the big frame and the two small frames.

Abstract: Systems and methods for storing, or caching, VC descriptors on a single-chip network processor to enhance system performance. The single-chip network processor includes an on-chip cache memory that stores VC descriptors for fast retrieval. When a VC descriptor is to be retrieved, a processing engine sends a VC descriptor identifier to a content-addressable memory (CAM), which stores VC descriptor identifiers in association with addresses in the cache where associated VC descriptors are stored. If the desired VC descriptor is stored in the cache, the CAM returns the associated address to the processing engine and the processing engine retrieves the VC descriptor from the cache memory. If the VC descriptor is not stored in the cache, the CAM returns a miss signal to the processing engine, and the processing engine retrieves the VC descriptor from an off-chip memory.

Abstract: Methods and apparatus are described for translating identifiers that are used by computers to reference various entities such as data structures, external objects, or connections in a telecommunications network, from a bulkier less manageable format to a smaller more manageable format. Such translations are carried out to reduce the needless processing and memory demands that are made of a localized set of components when the large identifiers the set receives from other components include fields that none of the members of the set need to access. The invention is centerd around a two-stage look-up method wherein an inputted external identifier is divided into two parts. The first part of the inputted external identifier is used as an address into a first look-up table that contains base-addresses of a second look-up table. The second part of the inputted external identifier is used as an offset-address into the second look-up table.

Abstract: A system and method for determining and providing reactive power compensation for an inductive load. A reactive power compensator (50,50') monitors the voltage and current flowing through each of three distribution lines (52a, 52b, 52c), which are supplying three-phase power to one or more inductive loads. Using signals indicative of the current on each of these lines when the voltage waveform on the line crosses zero, the reactive power compensator determines a reactive power compensator capacitance that must be connected to the lines to maintain a desired VAR level, power factor, or line voltage. Alternatively, an operator can manually select a specific capacitance for connection to each line, or the capacitance can be selected based on a time schedule. The reactive power compensator produces control signals, which are coupled through optical fibers (102/106) to a switch driver (110, 110') to select specific compensation capacitors (112) for connections to each line.

Abstract: This invention relates to a detachable stationery case rack and more particularly to the one which includes a polygonal bottom case divided into several receiving compartments defining therein a hollow central shaft for setting therein of a central column for further mounting thereon of stationery accessories receiving cases. The base of the stationery case rack has a packing set therein, which packing includes several round balls to permit rotation of the whole assembly against the base. Through series connection, the number of stationery receiving cases may be flexibly arranged according to requirement.