Abstract: A method of performing digital division includes right-shifting a divider to provide a temporary divider, subtracting the temporary divider from a temporary dividend to provide a difference, determining the temporary dividend based on at least one of a dividend and the difference, and left-shifting a quotient based on the difference. A corresponding computer-readable medium and device are provided. A system to perform digital division includes a counter and a division circuit. The counter provides a count, and the division circuit is operatively coupled to the counter. The division circuit divides a dividend by a divider to provide a quotient in response to the counter. At least one of the counter and division circuit is configured to accept at least one of the count, dividend, divider, and quotient with a configurable bit-width.

Abstract: A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.

Abstract: A method of performing digital division includes right-shifting a divider to provide a temporary divider, subtracting the temporary divider from a temporary dividend to provide a difference, determining the temporary dividend based on at least one of a dividend and the difference, and left-shifting a quotient based on the difference. A corresponding computer-readable medium and device are provided. A system to perform digital division includes a counter and a division circuit. The counter provides a count, and the division circuit is operatively coupled to the counter. The division circuit divides a dividend by a divider to provide a quotient in response to the counter. At least one of the counter and division circuit is configured to accept at least one of the count, dividend, divider, and quotient with a configurable bit-width.

Abstract: A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.

Abstract: Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector samples the clock signal and the reference signal on positive edges of one or more of the clock signal and the reference signal, samples the clock signal and the reference signal on negative edges of one or more of the clock signal and the reference signal, and generates one or more error signals indicating a phase difference between the clock signal and the reference signal. A clock signal that is phase aligned with a reference signal can be generated by generating an error signal indicating a phase difference between the clock signal and the reference signal and applying the error signal to an oscillator to produce the clock signal.

Abstract: A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contiguous clock signals from the set of phase-shifted clock signals. Each subset of contiguous clock signals is applied to a different set of one or more verniers, each vernier independently selecting one of the contiguous clock signals as its retiming clock signal for use in generating either (1) an output clock signal or a retimed bit of address or control data for one or more of the memory devices or (2) a feedback clock signal for the PLL-based clock generator. The SBR circuit can be designed to satisfy relatively stringent signal timing requirements related to skew and delay.

Abstract: Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector comprises a first logic circuit for (i) sampling the clock signal and the reference signal on positive edges of one or more of the clock signal and the reference signal, and (ii) generating one or more error signals indicating a phase difference between the clock signal and the reference signal; and a second logic circuit for (i) sampling the clock signal and the reference signal on negative edges of one or more of the clock signal and the reference signal, and (ii) generating one or more error signals indicating a phase difference between the clock signal and the reference signal.

Abstract: A digital filtering apparatus and method for digitally filtering out undesirable or invalid data from data signal lines. The digital filtering apparatus includes a digital delay element having one or more outputs, a comparator connected to the outputs of the digital delay element, and a final stage connected to the output of the comparator and the outputs of the digital delay element. The digital filtering apparatus recognizes and filters out invalid data from data received by the digital delay element, and allows valid data to pass through the filter. Data is considered invalid data if its logical data state transition has a duration less than the clock setting of the digital filtering apparatus. The clock setting can be established by the number of active delay components in the digital delay element. The inventive digital filtering apparatus represents an improvement over conventional analog filters, e.g., in manufacturing efficiency and filtering performance.

Abstract: Methods and apparatus are provided for loss-of-clock detection. A loss of a clock signal is detected by delaying the clock signal using one or more delay elements; and applying an output of the one or more delay elements to at least one logic gate having a plurality of inputs, wherein the at least one logic gate has a predefined binary output value when each of the inputs to the at least one logic gate have a predefined input binary value to detect when the clock signal is in a fixed binary position. The at least one logic gate can be an AND gate (or a NOR gate having inverted inputs) to detect when the clock signal is in a fixed high position. The at least one logic gate can also be a NOR gate (or an AND gate having inverted inputs) to detect when the clock signal is in a fixed low position. A third logic gate, such as an OR gate, can detect when at least one of two logic gates has a predefined binary output value.

Abstract: A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contiguous clock signals from the set of phase-shifted clock signals. Each subset of contiguous clock signals is applied to a different set of one or more verniers, each vernier independently selecting one of the contiguous clock signals as its retiming clock signal for use in generating either (1) an output clock signal or a retimed bit of address or control data for one or more of the memory devices or (2) a feedback clock signal for the PLL-based clock generator. The SBR circuit can be designed to satisfy relatively stringent signal timing requirements related to skew and delay.

Abstract: A method and apparatus implementing an enhanced protocol between an I2C master and an I2C slave. In various embodiments the invention permits greater addressability space and high priority access to the slave device. The enhanced protocol is implemented by the addition of command code data being transmitted which is recognized through an interface circuit inside the slave device. The invention provides an I2C solution for accessing high priority address space with one command byte, medium priority space with two command bytes and low priority space with three command bytes.

Abstract: A control circuit and method for controlling the electrical characteristics of an input/output (I/O) circuit such as an output driver to account for variations in fabrication process, supply voltage, and/or temperature (PVT) conditions includes a PVT controller having appropriate control logic to permit PVT compensation to be observed, tested, and selectively adjusted. The PVT controller permits selection between PVT sensing circuit-provided control signals and control signals stored in a hardware register for controlling drive strength. The PVT controller further provides the capability to offset the selected drive strength by a fixed amount and select whether or not the offset is applied and permits full testability and observability of the selected control signal, an offset value applied thereto, and the resulting output signal.

Abstract: The invention is a method and apparatus for minimizing power consumption in a computer peripheral device during suspend state and waking up from suspend state without losing pre-suspend configuration information. The power supply to the peripheral device is split into two power rails, namely, a first rail that is unswitched and a second rail that is switched. The switched power rail provides power to components of the peripheral device other than the bus interface circuit. The unswitched power rail provides power to the bus interface circuit. When the device enters suspend mode, first power is removed from the components other than the bus interface circuit, then all outputs from the other components of the peripheral device to the bus interface circuit and all of the outputs from the bus interface circuit to the other components are forced to logic level 0 so that they do not float during suspend mode, and then finally the clock is disabled.

Abstract: A circuit compensating for the difference in transmission rate of digital samples generated in transmit and receive paths between a user and a transceiver processing in the frequency domain, such as a digital multi-tone (DMT) transceiver. Compensation of the DMT transmission rate in the receive path in accordance with exemplary embodiments of the present employs zero-padding of the frequency domain coefficients generated by the DMT transceiver prior to applying an inverse transform, such as the inverse fast Fourier transform (IFFT). Zero-padding the frequency domain coefficients allows for the compensation of the transmission rate in the receive path by generating digital samples from the frequency domain coefficients with an inverse transform having a rate matched to the frequency domain transform and rate employed in the transmit path.

Abstract: A digital clock rate multiplier for multiplying the clock rate of an input signal to produce a multiplied output signal having a higher clock rate than the input signal. The digital clock rate multiplier includes a digital delay signal generator for developing first and second delay signals based on the input signal and a delayed version of the input signal, and a clock circuit for producing the multiplied output signal based at least partially on the first and second delay signals. The multiplied output signal may be used in high speed integrated circuits.

Abstract: The invention is a method and apparatus for minimizing power consumption in a computer peripheral device during suspend state and waking up from suspend state without losing pre-suspend configuration information. The power supply to the peripheral device is split into two power rails, namely, a first rail that is unswitched and a second rail that is switched. The switched power rail provides power to components of the peripheral device other than the bus interface circuit. The unswitched power rail provides power to the bus interface circuit. When the device enters suspend mode, first power is removed from the components other than the bus interface circuit, then all outputs from the other components of the peripheral device to the bus interface circuit and all of the outputs from the bus interface circuit to the other components are forced to logic level 0 so that they do not float during suspend mode, and then finally the clock is disabled.

Abstract: A digital clock rate multiplier for multiplying the clock rate of an input signal to produce a multiplied output signal having a higher clock rate than the input signal. The digital clock rate multiplier includes a digital delay signal generator for developing first and second delay signals based on the input signal and a delayed version of the input signal, and a clock circuit for producing the multiplied output signal based at least partially on the first and second delay signals. The multiplied output signal may be used in high speed integrated circuits.

Abstract: A dual processor system comprises a first processor coupled to a second processor by a system address bus and a data bus. The second processor has a control register having a control register system address, an internal memory, a data register having a data register system address and coupled to the internal memory, and an internal address generator coupled to the control register and to the internal memory. The control word is written into the control register when the first processor places a control word having a burst mode bit and a starting internal address on the data bus and asserts the control register system address on the system address bus. The second processor enters a burst mode in which the internal address generator selects consecutive memory locations of the internal memory, starting at the starting internal address specified in the control word stored in the control register, during subsequent data transfer cycles, when the control word has a burst mode bit indicating burst mode.

Abstract: The use of a JTAG port for boundary scan testing of integrated circuits, (IC) thereby allowing for the testing of the IC's after they have been mounted onto a circuit board. The present invention speeds the testing of integrated circuitry by introducing an external memory where all the test vectors are stored. This external memory is connected to the digital processor core by a high speed interface extended memory interface (EMI). The test vectors are uploaded into the digital processor core from the external memory via the high speed EMI interface.

Abstract: The present invention provides a synchronizing data protocol comprising one or more serial input-output (SIO) control word(s) and data passed across a high voltage interface, to allow the elimination of a frame synchronization signal (and corresponding AC coupling capacitors). The present invention has particular applicability to, e.g., time division multiplexed (TDM) data, serial data communication devices, or synchronous serial communication interfaces in general, and to the communication between a controller and a codec in an audio codec device in accordance with the AC '97 Specification, i.e., the AC Link. The synchronizing data protocol is implemented over a transmit data signal line to provide occasional synchronization (i.e., not frame-by-frame synchronization) between the two communicating devices. The master device includes a preamble insertion module to insert a predetermined preamble code word into the transmitted data stream.