Abstract: An apparatus for developing internal ROM code is disclosed for use in applications where software code is being developed for a ROM device inside a device and there is a need for the application to cause code from an external memory to be executed at the same time as internal ROM code. Accessing code from an external memory requires the use of the external bus interface. In order to free the external memory for use and the external bus interface for accessing code from external memory yet still allow testing of ROM code from an external memory before it is implemented on a ROM chip inside the device, an additional memory is used outside the device, and internal control logic is added.

Abstract: A 50% duty-cycle divided-down clock with selectable divisor rates. A simple architecture comprised of two n-bit counters, a state machine, 2 toggle flip-flops, and two 2-to-1 muxes is used to allow an input clock signal to be divided down by any divisor rate up to 2n.

Abstract: A digital power-up reset circuit is disclosed which provides a pulse of a predetermined width after a period of time after power-up. Because the power-up circuit is digital, it can be easily implemented in an integrated circuit. Moreover, it is relatively invariable to differences in manufacturing processes from device to device, in contrast to conventional analog (e.g., RC time constant based) power-up reset circuits, which have widely varied output pulses from device to device, and which are highly susceptible to variances in output pulse width due to changes in ambient temperature. The digital power-up reset circuit includes a first linear feedback shift register which starts up in an arbitrary state, and a second linear feedback shift register which defines a desired length of an activation of an output reset signal.

Abstract: An encoder which includes a flip-flop; a first, second and third NAND gate; a first and second inverter; and a first and second delay cell. The first inverter couples the flip-flop with the first NAND gate. The first delay cell couples the first NAND gate with the third NAND gate. The second inverter couples the second delay cell with the second NAND gate. Further, the second NAND gate couples the second inverter with the third NAND gate. The third NAND gate of the encoder produces a glitch-free encoded signal.