Patents by Inventor Toru Otsuka

Toru Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020113366
    Abstract: There is disclosed a processing apparatus of sheets using an accumulation device of a vaned wheel system including a vaned wheel having a plurality of blades arranged at a predetermined interval in a rotation direction, and rotating, thereby allowing continuously feed sheets to enter between the blades, and guiding the sheets in a predetermined direction, so that the sheets guided by the vaned wheel are laminated/accumulated in an accumulation section, and synchronization is established between a supply timing of paper money by a paper money supply section and a rotation phase of the vaned wheel.
    Type: Application
    Filed: December 21, 2001
    Publication date: August 22, 2002
    Inventors: Hiroshi Watanabe, Toru Otsuka, Kunio Fukatsu, Shigemi Kawamura
  • Publication number: 20020066637
    Abstract: A bank note processing apparatus comprises an insert port into which plural sheets of rectangular shaped bank notes having the front/back and top/bottom extending along the longitudinal direction a take-out portion for taking out the bank notes inserted into the insert port with the top or bottom laid ahead one by one, a conveying path which conveys the bank notes taken out of the insert port with the top or bottom laid ahead, a detector which detects information relative to the front/back and top/bottom of the bank notes being conveyed on the conveying path, a front/back reversing portion which selectively reverses the front/back of the bank notes being conveyed based on the result of detection in the detector, first and second stackers which stack the bank notes of which front/back are selectively reversed in the front/back reversing portion, a sorting portion which sorts the bank notes being conveyed on the conveying path to either the first or second stacker, and first and second banding portions which ba
    Type: Application
    Filed: October 18, 2001
    Publication date: June 6, 2002
    Inventors: Toru Otsuka, Morimasa Miyashita
  • Patent number: 6344802
    Abstract: A control system is disclosed which permits information captured by each sensor to be sent exactly to a main controller and a fall in the level of sensor signals with time to be automatically compensated for with no need to make sensor signal lines long and without reducing the sensor monitoring accuracy and limiting the number of sensors used. The levels of signals from sensors connected to each of unit controllers are compared with slice levels. The results of comparisons are converted into a serial signal and then transmitted to the main controller. Each time the sensor signal level is monitored, the optimum slice level therefor is set.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: February 5, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Otsuka, Takeo Hashimoto, Hiroshi Watanabe
  • Patent number: 6335603
    Abstract: Disclosed herein are a motor control circuits and a control system comprising the motor control circuits.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: January 1, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Otsuka, Takeo Hashimoto, Hiroshi Watanabe
  • Patent number: 6309458
    Abstract: This invention provides a method for fabricating a silicon thin film which is high in supply efficiency of silicon material. In the method for fabricating a silicon thin film by placing a silicon semiconductor single crystal substrate in a process vessel and by supplying a silicon material into the process vessel, a wall of the process vessel is cooled so that silicon tetrachloride (SiCl4) concentration in an exhaust gas discharged from the process vessel during a growth process of a silicon thin film becomes equal to or lower than {fraction (1/10)} of a concentration of the silicon material in the exhaust gas. Also, the wall of the process vessel is cooled so that temperature gradient between a surface of the semiconductor single crystal substrate and the wall of the process vessel satisfies the following Equation (1) in relation to a temperature of the semiconductor single crystal substrate: temperature gradient(K/cm)≧0.3×substrate temperature(K)−90  (1).
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: October 30, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Shoji Akiyama, Toru Otsuka
  • Publication number: 20010025235
    Abstract: A simulator has a simulation CPU and a memory having a plurality of memory areas which include memory areas write-accessible from a control CPU connected to the simulator and memory areas read-accessible from the simulation CPU. Control information written in the memory area by the control CPU is read out by the simulation CPU. The simulation CPU executes simulation on the basis of the control information and writes the execution result of the simulation in the memory.
    Type: Application
    Filed: March 13, 2001
    Publication date: September 27, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toru Otsuka
  • Patent number: 6245647
    Abstract: The invention provides a method for forming a thin film uniform in resistivity distribution on a semiconductor substrate. The temperature of the inside wall (6) of the reaction vessel (2) of vapor phase growth equipment is controlled to below the thermal decomposition temperature of a dopant gas such as diborane, for example, to within a range of room temperature to 250° C. The region of this temperature range is defined so as to range from the upstream-side end of the semiconductor substrate (1) to at least an upstream-side {fraction (1/3 )} point of the substrate diameter along the direction of flow of the dopant gas supplied from one end of the reaction vessel (2), desirably, over the entire region just above the semiconductor substrate (1).
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: June 12, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Shoji Akiyama, Toru Otsuka, Hitoshi Habuka
  • Patent number: 6235645
    Abstract: An object of the invention is to remove organic materials and metal impurities on a silicon-based semiconductor substrate while preventing regrowth of a natural oxide film and thermal diffusion of the metal impurities from occurring. In order to achieve the object, H2 gas that can maintain a reductive atmosphere is consistently used, as a carrier gas, through a whole process, the organic materials in attachment is decomposed by HF gas and the metal impurities are transformed into metal chlorides by HCl gas. In any of treatments, since products whose vapor pressures are higher than those of respective starting materials are obtained, the products are respectively vaporized in a H2 gas atmosphere at higher temperatures than those at which the decomposition and the transformation are performed. The whole process can be performed in a low temperature range whose upper limit is 1000° C. or lower.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: May 22, 2001
    Assignee: Shin Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Toru Otsuka
  • Patent number: 6194691
    Abstract: This invention provides a method of manufacturing a wafer heating furnace having a desired heating distribution with less trials and errors by predicting heating distributions in the process of designing the heating furnace.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: February 27, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Toru Otsuka
  • Patent number: 6124209
    Abstract: The surface of a silicon single crystal substrate 2 is exposed to a mixed gas of hydrogen fluoride gas and hydrogen gas at 0.degree. C.-100.degree. C. to remove a natural oxide film 3 formed on the surface of silicon single crystal substrate 2. The method, as a pre-treatment to the formation of a silicon single crystal thin film, gives a smooth surface with a low temperature treatment and without causing the out-diffusion of the dopants or the auto-doping phenomenon.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: September 26, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Toru Otsuka
  • Patent number: 6008128
    Abstract: A method for microscopically smoothing a surface of a wafer made of silicon single crystal having a low resistivity. In the method, a native oxide film grown on a surface of a wafer having polished by an ordinary mirror polishing process is removed at a temperature of less than 100.degree. C. with use of a mixture gas of HF and H.sub.2, and then an organic substance deposited thereon is removed at a temperature of less than 800.degree. C. with use of a mixture gas of HCl and H.sub.2. Re-growth of an oxide film is suppressed in a consistent H.sub.2 atmosphere, during which the wafer is substantially not varied in its surface roughness. Then the wafer is thermally treated in an H.sub.2 gas atmosphere at a temperature of not less than 800.degree. C. and less than 1000.degree. C.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: December 28, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Toru Otsuka, Masatake Katayama
  • Patent number: 5885346
    Abstract: Organic protective film 4 is directly adhered on the surface of silicon semiconductor crystal 1. Silicon semiconductor crystal 1 with organic protective film 4 is prepared by adhering organic protective film 4 on the surface of silicon semiconductor crystal substrate 1 on which oxide film 8 is formed, removing oxide film 8 to directly adhere organic protective film 4 on the surface of silicon semiconductor crystal 1, removing organic protective film 4 and then treating silicon semiconductor crystal 1.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: March 23, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Toru Otsuka
  • Patent number: 4694456
    Abstract: An information signal reproducing apparatus comprises a memory for storing encoded digital data and error correction data, and a decoder for decoding the digital data, producing decoded digital data organized in blocks, and delivering the decoded digital data one block at a time. A data transmission controller controls the transmission of the digital data from the memory to the decoder, and an analog signal processor forms a reproduced analog information signal in accordance with each block of the decoded digital data. A data supply controller controls the supply of each block of the decoded digital data to the analog signal processor.
    Type: Grant
    Filed: December 20, 1985
    Date of Patent: September 15, 1987
    Assignee: Sony Corporation
    Inventors: Kazuyuki Morita, Toru Otsuka
  • Patent number: 4674078
    Abstract: An optical information reproducing apparatus for reproducing an information recorded on a recording surface of a disc shape record medium is disclosed, which includes an optical pick-up device mounted on a tiltable optical block and having a laser beam source for generating a laser beam and a photo detector for detecting the refelected beam from the recording surface and for reproducing the recorded information, a device for rotating the record medium, a skew error detector for detecting a skew of the record medium relative to the optical pick-up device and for generating a skew error signal having a D.C. component and an A.C. component, a control circuit supplied with the skew error signal and for generating a control signal responsive to the D.C. component of the skew error signal, a skew error corrector controlled by the control signal and for controlling the optical block so that the optical axis of the pick-up device is maintained to be always perpendicular to the recording surface.
    Type: Grant
    Filed: December 21, 1984
    Date of Patent: June 16, 1987
    Assignee: Sony Corporation
    Inventors: Toru Otsuka, Tadashi Motoyama
  • Patent number: 4513334
    Abstract: A head positioning apparatus for an HVTR has two rotary heads mounted to a rotating drum by electrically deflectable bi-morph leaves. To trace tracks on the tape when the tape is played back at a speed different from that used to record it, tracking correction signals are repeatedly applied to the bi-morph leaves to deflect the heads into position to trace the tracks properly. Residual deflection in the bi-morph leaves, when the tracking correction signals terminate at the end of each trace, is removed by a hysteresis-erasing signal that flexes the bi-morph leaf back and forth. The polarity of the hysteresis-erasing signal depends on whether the tape on playback is running faster or slower than the recording speed.
    Type: Grant
    Filed: March 29, 1983
    Date of Patent: April 23, 1985
    Assignee: Sony Corporation
    Inventor: Toru Otsuka