Abstract: An embodiment of a solar cell is provided comprising a silicon substrate, on a first surface of which a texture structure including mountain portions and valley portions is formed, and an amorphous silicon layer provided on the first surface of the silicon substrate. The texture structure, in a cross section passing through the mountain portions and the valley portions, includes pairs of slant portions, each pair slanting to extend from a pair of neighboring ones of the mountain portions toward the valley portion therebetween while coming closer to each other. The valley portion located between the slant portions is in a round shape with a radius of curvature of 150 nm or smaller. The amorphous silicon layer includes an epitaxial growth area grown from the valley portion, the epitaxial growth area on the valley portion is thicker than that on a region other than the valley portion.

Abstract: Disclosed is a solar cell module including: a plurality of solar cell units each including a supporting substrate 30 and an even number of solar cells 20 disposed on the supporting substrate 30; and a conductor 10 configured to electrically connecting surfaces of adjacent solar cells 20 that have opposite surface polarities and are formed in respective solar cell units adjacent to each other. The solar cells 20 having the opposite surface polarities are alternately arranged in each of the solar cell units so that the surface polarities of the adjacent solar cells 20 are opposite to each other, and the solar cell unit has one or more sets of two solar cells electrically connected to each other on the supporting substrate 30.

Abstract: Provided is a method for evaluating a solar cell incorporated into a solar module. A PL evaluation step is performed. The PL evaluation step is a step for evaluating the solar cell to be evaluated among a plurality of solar cells (10) by illuminating the solar cell (10) with light from a light source (20) and detecting the intensity of photoluminescent light (L2) emitted by the solar cell (10). The light is irradiated while a light-blocking member (21) is provided between the solar module (1) and the light source (20) so that light from the light source (20) is not incident on portions of the solar module other than the solar cell (10) to be evaluated.

Abstract: This photovoltaic device is provided with a crystalline semiconductor substrate, and a first amorphous layer formed on the main surface of the substrate. At the interface between the substrate and the first amorphous layer, electrical conductivity can be improved while suppressing an increase in recombination centers, and power generation efficiency can be improved by having a p-type dopant density profile that decreases stepwise in the film thickness direction from the vicinity of the interface with the substrate.

Abstract: Provided is a method for evaluating a solar cell incorporated into a solar module. A PL evaluation step is performed. The PL evaluation step is a step for evaluating the solar cell to be evaluated among a plurality of solar cells (10) by illuminating the solar cell (10) with light from a light source (20) and detecting the intensity of photoluminescent light (L2) emitted by the solar cell (10). The light is irradiated while a light-blocking member (21) is provided between the solar module (1) and the light source (20) so that light from the light source (20) is not incident on portions of the solar module other than the solar cell (10) to be evaluated.

Abstract: A photovoltaic device is provided with: an i-type amorphous layer formed over a region of at least a part of a back surface of a semiconductor substrate; and an i-type amorphous layer formed over a region of at least a part of a light-receiving surface of the semiconductor substrate. No electrode is provided on the light-receiving surface, and an electrode is provided on the back surface. An electrical resistance per unit area of the i-type amorphous layer is lower than an electrical resistance per unit area of the i-type amorphous layer.

Abstract: A solar battery cell and a solar battery module are provided with improved photoelectric conversion efficiency. An electrode (21a) includes a plurality of linear electrode portions (31) and trapezoidal electrode portions (32a, 32b). The trapezoidal electrode portions (32a, 32b) are provided in end portions (20a2, 20a3). The trapezoidal electrode portions (32a, 32b) include upper floor portions (32a1, 32b1), lower floor portions (32a2, 32b2), and pairs of oblique portions (32a3, 32a4, 32b3, 32b4). The pairs of oblique portions (32a3, 32a4, 32b3, 32b4) connect the end portions of the upper floor portions (32a1, 32b1) to the end portions of the lower floor portions (32a2, 32b2).

Abstract: A solar cell includes a crystalline Si layer including a pn junction and a semiconductor layer formed on a first main surface of the crystalline Si layer. The semiconductor layer has the same conductivity as a portion of the crystalline Si layer that is in contact with the semiconductor layer. The open circuit voltage under light irradiation onto the solar cell is different from a level difference between the quasi Fermi level of electrons and the quasi Fermi level of holes in the crystalline Si layer.

Abstract: An aspect of the invention provides a solar cell that comprises a semiconductor substrate having a light-receiving surface and a rear surface; a first semiconductor layer having a first conductivity type; a second semiconductor layer having a second conductivity type, the first semiconductor layer and the second semiconductor layer being formed on the rear surface, and a trench formed in the rear surface, wherein the first semiconductor layer is formed on the rear surface in which the trench is not formed, and the second semiconductor layer is formed on a side surface of the trench in an arrangement direction in which the first semiconductor layer and the second semiconductor layer are alternately arranged and on a bottom surface of the trench.

Abstract: Provided is a stress measurement kit that is economical and that has good sensitivity. The stress measurement kit for measuring a stress level of a test subject includes: (A) a sensor chip including an electrically insulating substrate, and an electrode system that is placed on the electrically insulating substrate and that includes at least a working electrode and a counter electrode, wherein glucose dehydrogenase (GDH) and an electron mediator are immobilized on the working electrode; (B) a polysaccharide; and (C) a sensor body including an insertion hole into which the sensor chip is inserted, an electrical measurement means that is electrically connected to the electrode system of the sensor chip in a state where the sensor chip is inserted into the insertion hole, and a conversion means by which a current value or an electric quantity measured by the electrical measurement means is converted into an amylase activity value.

Abstract: Solar cells and methods of their manufacture are described that exhibit decreased or eliminated leak current, improved open voltage and improved fill factor characteristics. In an embodiment, a separate processed surface is interposed between a first and a second main surface of a crystal substrate, as prepared by laser irradiation and cut processing. The laser irradiation is applied to an amorphous semiconductor layer of the same conductive type as an underlying single crystal substrate, but does not penetrate an underlying amorphous opposite type layer. Details of lamination and laser characteristics for processing the layers are provided.

Abstract: The present invention provides a test circuit for a semiconductor integrated circuit that can be used for testing plural of logic blocks each having plural input-output terminals. This test circuit is provided with scanning flip-flop (SFF) circuits whose output terminals are connected to the input terminals of the logic blocks. The SFF circuits hold test data which is sequentially supplied, supply the test data to the logic blocks and receive logic operation data generated from the logic blocks. The logic operation data may be sequentially supplied from the SFF circuits, on the basis of which performances of the logic blocks are examined.

Abstract: A convenient, inexpensive wrist blood pressure gauge whereby a cuff can easily be adjusted to the height of the heart merely by adding a simple structure. A lenticular sheet (display body (14)) whose visible image varies according to an angle in relation to a sight line (S) of a measurement subject is provided to a wrist blood pressure gauge (1) worn on a wrist (Mt) of the measurement subject (M), wherein a specific image is visible to the eyes (Ma) of the measurement subject when the wrist is set at the correct height in relation to the heart (H), and a different image is visible to the eyes of the measurement subject when the wrist is not in an appropriate height range.

Abstract: Disclosed is a solar cell module including: a plurality of solar cell units each including a supporting substrate 30 and an even number of solar cells 20 disposed on the supporting substrate 30; and a conductor 10 configured to electrically connecting surfaces of adjacent solar cells 20 that have opposite surface polarities and are formed in respective solar cell units adjacent to each other. The solar cells 20 having the opposite surface polarities are alternately arranged in each of the solar cell units so that the surface polarities of the adjacent solar cells 20 are opposite to each other, and the solar cell unit has one or more sets of two solar cells electrically connected to each other on the supporting substrate 30.

Abstract: A convenient, inexpensive wrist blood pressure gauge whereby a cuff can easily be adjusted to the height of the heart merely by adding a simple structure. A lenticular sheet (display body (14)) whose visible image varies according to an angle in relation to a sight line (S) of a measurement subject is provided to a wrist blood pressure gauge (1) worn on a wrist (Mt) of the measurement subject (M), wherein a specific image is visible to the eyes (Ma) of the measurement subject when the wrist is set at the correct height in relation to the heart (H), and a different image is visible to the eyes of the measurement subject when the wrist is not in an appropriate height range.

Abstract: The present invention provides a test circuit for a semiconductor integrated circuit that can be used for testing plural of logic blocks each having plural input-output terminals. This test circuit is provided with scanning flip-flop (SFF) circuits whose output terminals are connected to the input terminals of the logic blocks. The SFF circuits hold test data which is sequentially supplied, supply the test data to the logic blocks and receive logic operation data generated from the logic blocks. The logic operation data may be sequentially supplied from the SFF circuits, on the basis of which performances of the logic blocks are examined.

Abstract: An ITO film as a transparent conductive film is formed on a semiconductor layer comprising an amorphous semiconductor or a microcrystalline semiconductor, a comb-like collecting electrode is formed on the ITO film, and a cover glass containing alkaline ions is placed on the ITO film and collecting electrode with a resin film made of EVA between them. The (222) plane orientation degree of the ITO film (transparent conductive film) is not less than 1.0, preferably not less than 1.2 and not more than 2.6, and more preferably not less than 1.4 and not more than 2.5. Alternatively, the transparent conductive film has an orientation of (321) planes on the boundary side with respect to the semiconductor layer and mainly an orientation of (222) planes in the remaining portion. When the total thickness of the ITO film is 100 nm, the (321)/(222) diffraction strength ratio in a 10 nm-thick portion on the semiconductor layer side is not less than 0.5 and not more than 2.5.

Abstract: Solar cells and methods of their manufacture are described that exhibit decreased or eliminated leak current, improved open voltage and improved fill factor characteristics. In an embodiment, a separate processed surface is interposed between a first and a second main surface of a crystal substrate, as prepared by laser irradiation and cut processing. The laser irradiation is applied to an amorphous semiconductor layer of the same conductive type as an underlying single crystal substrate, but does not penetrate an underlying amorphous opposite type layer. Details of lamination and laser characteristics for processing the layers are provided.

Abstract: A solar cell module capable of suppressing reduction of output characteristics by suppressing reduction of the quantity of light incident upon solar cells is provided. This solar cell module comprises a light reflective member, arranged on a region of a surface of a first translucent member opposite to an incidence side corresponding to a space between solar cells, having a corrugated light reflective surface on a side closer to the first translucent member. A second translucent member having a refractive index higher than that of the first translucent member is embedded in at least recess portions of the corrugated light reflective surface of the light reflective member.

Abstract: There is provided a method of designing a conductive pattern layout between a plurality of blocks in an LSI, the conductive pattern transferring data from one block to the other blocks, comprising: (a) extracting the blocks from logic circuit data; (b) preparing a floor plan which defines a provisional arrangement of the blocks; (c) arranging a plurality of conductive pattern cells between the plurality of blocks after preparing the floor plan; (d) re-arranging the blocks on the basis of the arrangement of the conductive pattern cells; (e) arranging a plurality of power source patterns; and (g) arranging a plurality of signal patterns. Due to this conductive pattern layout and method of designing thereof, wiring between blocks can be carried out simply and with high accuracy.