Abstract: A variable gain amplifying apparatus has an amplifier, one or more first switching elements connected in parallel to the amplifier, and a phase shifter connected in series to the first switching element. The first switching element is enabled if the level of an input signal or an output signal is higher than a predetermined level, and the first switching element is disabled if the level of the input signal or the output signal is equal to or lower than the predetermined level. The amplifier does not operate when the first switching element is enabled, and the amplifier operates when the first switching element is disabled, and the amount of phase shift when the input signal is passed through the amplifier and phase shifter is substantially equal to the amount of phase shift when the input signal is passed through the first switching element.

Abstract: A semiconductor differential circuit comprising a semiconductor substrate, a first semiconductor device on the semiconductor substrate having a gate electrode for having one of differential signals conveyed thereto and a drain electrode for outputting one of the differential signals controlled by the gate electrode, a second semiconductor device formed on the semiconductor substrate having a gate electrode for having the other of the differential signals conveyed thereto and a drain electrode for outputting the other of the differential signals controlled by the gate electrode, and wherein the drain electrode and drain electrode are placed in the proximity so that, at a predetermined frequency, it is equivalent to the one in which the drain electrode is grounded via a predetermined resistance, and the drain electrode is grounded via the predetermined resistance.

Abstract: A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

Abstract: A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

Abstract: A cathode ray tube includes an electron gun for emitting at least one electron beam; a mask frame include a mask having a plurality of holes or slits for allowing the electron beam to be transmitted therethrough and a frame to which the mask is attached; and a panel including a phosphor layer to be scanned by the at least one electron beam transmitted through the plurality of holes or slits of the mask. The panel includes a plurality of stud pins for supporting the frame. The frame includes a plurality of elastic supports engaged with the plurality of stud pins. At least one of the plurality of elastic supports includes an engagement portion having an engaging hole which is engaged with one of the plurality of the stud pins and an elastic portion in contact with the one stud pin. Mask frame vibration causes the elastic portion to rub against a respective stud pin so as to generate a frictional force for attenuating the vibration of the mask frame.

Abstract: A multistage amplifying device for amplifying a desired signal comprise first to N-th amplifiers connected in cascade,wherein the k-th (k is 1 to N) amplifier includes a k-th amplification section; and a k-th feedback section which has a reactance component, changes a phase of a signal output from the k-th amplification section. When a phase difference between the desired signal output from the N-th amplifier and a third-order inter-modulation distortion(IM3) output from the (N-1)-th amplifier is referred to as a first phase, and a phase difference between the desired signal output from the N-th amplifier, and a combined IM3 obtained by combining a IM3 occurring in the N-th amplification section and a IM3 fed back from the N-th feedback section is referred to as a second phase, a difference between the first phase and the second phase is 120° or more and 180° or less.

Abstract: A frequency conversion circuit is provided capable of suppressing noise converted from about a frequency twice as large as a local signal to a reception band frequency, which performs modulation by mixing an input signal with a local signal. The frequency conversion circuit includes a first transistor whose base is electrically connected with one of a first input terminal pair inputted with the input signal; a second transistor whose base is electrically connected with the other of the first input terminal pair; third and fourth transistors whose emitters are electrically connected respectively with a collector of the first transistor; fifth and sixth transistors whose emitters are electrically connected respectively with a collector of the second transistor; and a differential noise suppression circuit provided between the collector of the first transistor and the collector of the second transistor.

Abstract: With an antenna duplexer having balanced terminals, there has been a problem that the amount of leakage of common-mode signal components in the balanced terminals is large. A balanced high-frequency filter designed to solve this problem comprises a balanced high-frequency element and a phase-shifting circuit which includes a transmission line and placed between output terminals, and which is series resonance circuit having a length set to ?T/2 (?T: the wavelength at a frequency in a transmission frequency band) and capable of resonating with common-mode signal components at a predetermined frequency.

Abstract: A balanced high-frequency device includes a balanced element; at least one balanced terminal connected to the balanced element; a phase circuit having at least first, second, and third impedance elements, and electrically connected between the balanced element and the balanced terminal. The first impedance element and the second impedance element are connected between the balanced terminals in series, the connection point between the first impedance element and the second impedance element is grounded through the third impedance element, a series resonant circuit is formed by the first impedance element and the third impedance element. A series resonant circuit is formed by the second impedance element and the third impedance element, and an impedance to a differential signal component in the passing band of the balanced elements of the first and second impedance elements is set so as to increase to the ground plane.

Abstract: In a differential capacitor1, first and second capacitors 1003 and 1004 are formed in substantially symmetrical positions from each other with respect to a vertical plane B-B?, on a semiconductor substrate 1020. The differential capacitor 1 further includes a shield plate 1022 interposed between the semiconductor substrate 1020 and the lower electrodes 1016 and 1018. When each of the lower electrodes 1016 and 1018 is projected onto the shield plate 1022 along the vertical direction, each projected lower electrode 1016 or 1018 has a partial overlap with the shield plate 1022.

Abstract: A transformer element 1 is formed on a semiconductor substrate using first and second wiring layers arranged parallel to each other in a vertical direction, and includes a first inductor 2 and a second inductor 3. The first and second inductors 2 and 3 are each provided using the first and second wiring layers such that if projected into one of the first and second wiring layers either along a vertical upward direction or a vertical downward direction, outlines of a projection form a symmetrical shape with respect to a predetermined reference plane, and portions corresponding to intersections between the outlines of the projection on the wiring layer are formed so as to be out of contact with each other.

Abstract: A low-noise differential bias circuit is provided which obtains excellent noise characteristics while ensuring excellent distortion characteristics. A collector of a transistor Q11 is connected to a voltage supply point (Vcc) via a resistor R15. A base of the transistor Q11 is connected to a base of a transistor Q1 via resistors R13, R11 connected in series. A connection point between the resistors R11, R13 is connected to the collector of the transistor Q11. A collector of a transistor Q12 is connected to the voltage supply point at connection point A via a resistor R16. A base of the transistor Q12 is connected to a base of a transistor Q2 via resistors R14, R12 connected in series. A connection point between the resistors R12, R14 is connected to the collector of the transistor Q12. By this configuration, a high frequency ground is performed at the connection point A.

Abstract: In a thermal head provided with a resistance layer having a plurality of heating element portions which generate heat by energization, an insulating barrier layer which determines the two-dimensional size of each heating element portion by covering each heating element portion, and electrode layers electrically connected to two end portions of each of the plural heating element portions, in the length direction of the resistance, a heat transfer layer is disposed on at least the insulating barrier layer to determine the two-dimensional surface exposure area of the insulating barrier layer by covering part of the insulating barrier layer and to dissipate the heat generated from the plural heating element portions, and surface exposure regions of the insulating barrier layer are specified as effective heating regions of the plural heating element portions by adjusting the two-dimensional size of the heat transfer layer.

Abstract: A high frequency (HF) semiconductor device includes a semiconductor substrate. An electroconductor layer is provided on the semiconductor substrate. A first insulator layer electrically insulates the electroconductor layer from the semiconductor substrate. N pieces of wires are provided on the semiconductor substrate, and N-phase signals (where N represents a positive integer greater than 2) are fed to the wires. A second insulator layer electrically insulates the wires from the electroconductor layer and the semiconductor substrate. N1 pieces of the wires are provided on one side of the electroconductor layer (where N1 represents 0 or a positive integer equaling or less than N). N2 pieces of the wires are provided on the other side of the electroconductor layer (where N2 represents 0 or a positive integer satisfying N1+N2=N).

Abstract: A balanced high-frequency device is constituted by a balanced device and a phase circuit. The input side of the balanced device is connected to an input terminal IN serving as an unbalanced input/output terminal and the output side of it is connected to output terminals OUT1 and OUT2 serving as balanced input/output terminals. Moreover, the phase circuit is connected between the output terminals.

Abstract: An amplifier circuit (15) amplifies a differential signal supplied by a pair of input terminals ( {P1+, P1?}). A phase controller circuit (25) is placed between the emitters of bipolar transistors (101a, 101b) and the ground. A feedback circuit (35) is placed across the input and the output of the amplifier circuit (15) for feeding the output of the amplifier circuit (15) back to the input thereof. A phase change amount in the amplifier circuit (15) is determined by the values of inductors (201a, 201b), whereas a phase change amount in the feedback circuit (35) is determined by the values of resistances (301a, 301b) and capacitors (302a, 302b). The values of these devices are selected so that a phase difference between an input signal and a feedback signal is approximately 180 degrees in a range from the frequency of a fundamental wave of the input signal to the frequency of a second harmonic thereof.

Abstract: A high-Q inductor for high frequency, having a plurality of inductor elements formed in a plurality of IC wiring layers with a connection formed therebetween. The directions of the magnetic fields generated by the respective inductor elements are substantially the same. With this construction, the section of the inductor is increased reducing the serial resistance component and an influence of a skin effect in a high-frequency range is eliminated increasing the Q value.

Abstract: An amplifier circuit 10 amplifies a signal inputted from an input terminal P1. A first feedback circuit 20 is placed across an emitter of a bipolar transistor 101 and an input of the amplifier circuit 10. A second feedback circuit 30 is placed across the input and an output of the amplifier circuit 10 for feeding the output of the amplifier circuit 10 back to the input. A phase change amount in the feedback circuit is determined by the values of an inductor and a capacitor. The values of these elements are selected so that a phase of a signal in which fundamental waves included in two feedback signals are combined and a phase of a signal in which second harmonics included in the two feedback signals are combined are shifted by approximately 180 degrees from a phase of a fundamental wave of an input signal.

Abstract: A high frequency switch circuit device includes an FET to be a switching element on a semiconductor substrate. The FET includes an n-type well, a gate electrode, a source layer and a drain layer. An n-type well line to be connected to an n-type well layer to be a back gate is connected to a voltage supply node via an inductor. The flow of a high frequency signal between the voltage supply node and the n-type well layer is blocked by the inductor, and the flow of a high frequency signal in the vertical direction is blocked by a depletion layer extending between the n-type well and a p-type substrate region. Moreover, the flow of a high frequency signal in the horizontal direction is blocked by a trench separation insulative layer.

Abstract: A welding route of welding a color selecting electrode to a frame is as follows: first of all, a welding head moves down onto one end portion of a long frame side (Step I), welding is conducted from the end portion toward a center portion of the long frame side (Step II). Then, after moving up once (Step III), the welding head moves horizontally toward the other end portion of the long frame side (Step IV) and moves down onto the long frame side (Step V), and welding is conducted from the other end portion toward a center portion of the long frame side (Step VI). Finally, the welding head retracts (Step VII). With this welding route, the generation of wrinkles in the vicinity of the end portions of the long sides of the color selecting electrode can be suppressed.