Abstract: A vending machine has a support part that has a first support member extending in the right and left direction on the inside of a commodity storage chamber and a second support member extending in the front and rear direction on the inside of the commodity storage chamber, and supports a commodity column so that the commodity column is movable in the front and rear direction on the first and second support members. In the vending machine, when a support receiving part is detached from the first support member, the commodity column can be moved in the front and rear direction via the second support member, so that replenishment of commodities to the commodity column and maintenance of the commodity column can be accomplished. Both of the first support member and the second support members are located under the commodity column, and support the commodity column from the downside. Therefore, spaces for arranging support members at the right and left of the commodity column are unnecessary.

Abstract: A vending machine has a support part that has a first support member extending in the right and left direction on the inside of a commodity storage chamber and a second support member extending in the front and rear direction on the inside of the commodity storage chamber, and supports a commodity column so that the commodity column is movable in the front and rear direction on the first and second support members. In the vending machine, when a support receiving part is detached from the first support member, the commodity column can be moved in the front and rear direction via the second support member, so that replenishment of commodities to the commodity column and maintenance of the commodity column can be accomplished. Both of the first support member and the second support members are located under the commodity column, and support the commodity column from the downside. Therefore, spaces for arranging support members at the right and left of the commodity column are unnecessary.

Abstract: A commodity column for a vending machine in which commodities are arranged in a front-rear direction, a plurality of the commodity columns being placed in a left-right direction in a commodity accommodation chamber, the commodity column having commodity passage members each having a side wall extending in the front-rear direction and a bottom extending from the side wall in one direction along the left-right direction, the commodity passage members being capable of being connected to each other through an extending end of the bottom, and a passage side member capable of being connected to the extending end of the bottom of the commodity passage member. A plurality of the commodity passage members are placed one after another in one direction along the left-right direction, each adjacent pair of the commodity passage members being connected to each other through the extending end.

Abstract: The present invention provides a commodity carrying out device that can reliably carry out even a commodity with a vertically long shape to a predetermined commodity carrying out position without producing a carrying-out failure. That is, when a bucket unit that receives a commodity is moved in a width direction towards a predetermined commodity carrying out position, the commodity is retained in an inclined state. It is thus possible to retain the commodity in a stable posture in the bucket unit that moves towards the predetermined commodity carrying out position, and even when carrying out a commodity that has a vertically long shape, the commodity can be reliably carried out to the commodity outlet portion without producing a carrying-out failure.

Abstract: The present invention provides a commodity carrying out device that can reliably carry out a vertically-long shaped commodity in an upright state from a commodity storage column to a bucket. More specifically, since a commodity positioned at the front end side of a commodity storage column is tilted forward to be moved into a bucket, when moving a vertically-long shaped commodity in an upright state into a bucket, it is possible to move the commodity without the commodity toppling backwards. Thus, the commodity can be reliably moved into the bucket.

Abstract: An apparatus for conveying and storing articles comprises an inlet/outlet slot, a plurality of storage spaces stacked vertically and transversely, and a movable bucket for conveying an article from the inlet/outlet slot to one of the storage spaces and conveying an article from one of the storage spaces to the inlet/outlet slot. The bucket comprises a bucket body, an arm projecting from the bucket body, a first driving roller provided on the arm and a guide projecting from the bucket body. The first driving roller and the guide enter one of the storage spaces to clamp an article, thereby enabling the article to be transferred from the bucket into the storage space and be taken from the storage space into the bucket.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The method begins with a processor determining which load to select for measurement. In response to the determination, the cycle counter value is stored in a rewind register. The processor issues the load and begins counting cycles. In response to the load completing, the level of memory for the load is determined. If the load was executed from the desired memory level, the load counter is incremented. Otherwise, the cycle counter is rewound to its previous value.

Abstract: A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of instructions has a status indicator that identifies what is preventing that instruction from completing execution. Examples of completion delays are cache misses, data dependencies or simply the time required for an execution unit in the computer processor to process the instruction. As each instruction finishes executing, its associated status indicator is cleared to indicate that the instruction is no longer waiting to execute. The last instruction to execute is the instruction that is holding up completion of the entire group, and thus the cause for the completion delay of the last instruction is recorded as the cause of completion delay for the entire group.

Abstract: An information processing system which includes a main memory, a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in the main memory, an internal cache controlled as a first level cache, and a cache control function which controls an external cache external of the processing unit as a second level cache. The prefetch instruction, when executed, causes the processing unit to selectively perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the first and second level caches or the second level cache only, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.

Abstract: An information processing system includes a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in a main memory two hierarchical level caches connected to the processing unit and the main memory as arranged so that a primary cache close to the processing unit is a first level cache, and a secondary cache close to the main memory is a second level cache. The prefetch instruction, when executed, causes the processing unit to perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the two hierarchical level data caches, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.

Abstract: A method and system for analyzing cycles per instruction (CPI) performance in a processor. A completion table corresponds to the instructions in a group to be processed by the processor. An empty completion table indicates that there has been some type of catastrophe that caused a table flush. While the table is empty, a performance monitoring counter (PMC), located in a performance monitoring unit (PMU) in the processor, counts the number of clock cycles that the table is empty. Preferably, a separate PMC is utilized depending on the reason that the completion table is empty. A second PMC likewise counts the number of clock cycles spent re-filling the empty completion table. A third PMC counts the number of clock cycles spent actually executing the instructions in the completion table. The information in the PMC's can be used to evaluate the true cause for degradation of CPI performance.

Abstract: A circuit and method for maintaining a correct value in performance monitor counter within a speculative computer microprocessor is disclosed. In response to determining the begin of speculative execution within the microprocessor, the value of the performance monitor counter is stored in a rewind register. The performance monitor counter is incremented in response to predetermined events. If the microprocessor determines the speculative execution was incorrect, the value of the rewind register is loaded into the counter, restoring correct value for the counter.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A method and system for analyzing cycles per instruction (CPI) performance in a processor. A completion table corresponds to the instructions in a group to be processed by the processor. An empty completion table indicates that there has been some type of catastrophe that caused a table flush. While the table is empty, a performance monitoring counter (PMC), located in a performance monitoring unit (PMU) in the processor, counts the number of clock cycles that the table is empty. Preferably, a separate PMC is utilized depending on the reason that the completion table is empty. A second PMC likewise counts the number of clock cycles spent re-filling the empty completion table. A third PMC counts the number of clock cycles spent actually executing the instructions in the completion table. The information in the PMC's can be used to evaluate the true cause for degradation of CPI performance.

Abstract: A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of instructions has a status indicator that identifies what is preventing that instruction from completing execution. Examples of completion delays are cache misses, data dependencies or simply the time required for an execution unit in the computer processor to process the instruction. As each instruction finishes executing, its associated status indicator is cleared to indicate that the instruction is no longer waiting to execute. The last instruction to execute is the instruction that is holding up completion of the entire group, and thus the cause for the completion delay of the last instruction is recorded as the cause of completion delay for the entire group.

Abstract: A circuit and method for maintaining a correct value in performance monitor counter within a speculative computer microprocessor is disclosed. In response to determining the begin of speculative execution within the microprocessor, the value of the performance monitor counter is stored in a rewind register. The performance monitor counter is incremented in response to predetermined events. If the microprocessor determines the speculative execution was incorrect, the value of the rewind register is loaded into the counter, restoring correct value for the counter.

Abstract: A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The method begins with a processor determining which load to select for measurement. In response to the determination, the cycle counter value is stored in a rewind register. The processor issues the load and begins counting cycles. In response to the load completing, the level of memory for the load is determined. If the load was executed from the desired memory level, the load counter is incremented. Otherwise, the cycle counter is rewound to its previous value.