Abstract: For improving the performance of an information processing unit having caches, indication bits for indicating a hierarchical level of a cache to which an operand data is to be transferred or for indicating a quantity of an operand data to be transferred or for indicating both are provided in a software prefetch instruction, and at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: For improving the performance of an information processing unit having caches, indication bits for indicating a hierarchical level of a cache to which an operand data is to be transferred or for indicating a quantity of an operand data to be transferred or for indicating both are provided in a software prefetch instruction, and at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction.

Abstract: An information processing system including a processing device for controlling hierarchical level data cache memories in response to execution of a prefetch instruction. The prefetch instruction includes indication bits for indicating a quantity of an operand data to be transferred from a main memory to an external cache, each being external of the processing device. The transferred operand data is used in a subsequent load instruction from the main memory to the external cache only, not to the internal cache, prior to executing the subsequent load instruction.

Abstract: A processing device for controlling hierarchical level data cache memories in response to execution of a prefetch instruction. The prefetch instruction includes indication bits for indicating a quantity of an operand data to be transferred from a main memory to an external cache, each being external of the processing device. The transferred operand data is used in a subsequent load instruction from the main memory to the external cache only, not to the internal cache, prior to executing the subsequent load instruction.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: For improving the performance of an information processing unit having caches, indication bits for indicating a hierarchical level of a cache to which an operand data is to be transferred or for indicating a quantity of an operand data to be transferred or for indicating both are provided in a software prefetch instruction, and at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction.

Abstract: For improving the performance of an information processing unit having caches, indication bits for indicating a hierarchical level of a cache to which an operand data is to be transferred or for indicating a quantity of an operand data to be transferred or for indicating both are provided in a software prefetch instruction, and at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction.

Abstract: An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be transferred, or both. The indication bits are provided in a software prefetch instruction such that at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction. Thus, it is not necessary to change the timing for executing a software prefetch instruction depending on which one of the caches of the hierarchical levels is hit, and a compiler can generate an instruction sequence more easily.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A cache memory apparatus that enables cache misses in the event of cache block conflict to be reduced and a cache memory situation to be easily inferred from outside, and a high-performance data processing system that uses this. There is provided a cache memory apparatus 5 having two cache memories that do not have an inclusive relationship between a processor 1 and lower-level memory 9 such as L2 cache memory or a main memory apparatus. Data transfer is controlled explicitly by software for one cache (naked cache) 6, and data that causes a cache-miss is transferred to the other cache (cache-miss cache) 7. Thereby, it is possible to provide a cache that is easily controlled by software, and to minimize a cache-miss penalty when explicit control by software is not possible.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: In an article providing apparatus, a storage rack (1) has a front face through which articles are loaded in the storage rack. The front face of the storage rack is covered by a covering member having a sample showcase (4) for showing a sample. The sample showcase is displaceable to enable the front face of the storage rack be exposed.

Abstract: An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indicator or indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be transferred, or both. The indication bits are provided in a software prefetch instruction such that at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction. Thus, it is not necessary to change the timing for executing a software prefetch instruction depending on which one of the caches of the hierarchical levels is hit, and a compiler can generate an instruction sequence more easily.

Abstract: A multiple focal lens is provided with: a diffraction element having a light incident surface and a light outgoing surface for diffracting a light beam incident from the external to the light incident surface and generating a plurality of diffraction light beams from the light outgoing surface; a light condense element for condensing the generated diffraction light beams respectively onto a plurality of focal points different in position from each other; and a main body for holding said diffraction element and said light condense element.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: An optical pickup for reproducing information on a disc has a pickup body mounting an optical system and a yoke base mounting an actuator. The pickup body and the yoke base are made of the same magnetic material.

Abstract: An optical pickup has a suspension base, a holder suspended from the suspension base by wires in a form of a cantilever, an optical system provided in the holder and having a mirror and an objective mounted in a body, and a flexible wiring plate connected between the holder and the suspension base. Effective length of the flexible wiring plate for focusing is approximately equal to suspension effective length of the wire. The flexible wiring plate comprises a pair of horizontal planes perpendicular to focusing direction and a vertical plane perpendicular to tracking direction provided between the horizontal planes.

Abstract: A pair of driving coils each having a focusing coil and a driving coil are arranged such that the focusing coils, and the tracking coils, of each of the driving coils are attached on opposite side surfaces of an optical-parts holder in a manner so that the focusing coils, and tracking coils, are symmetrically disposed both bilaterally and vertically with respect to the center of gravity of the optical-parts holder.

Abstract: An optical pickup has a suspension base, a holder suspended from the suspension base by wires in a form of a cantilever. The optical pickup is slidably mounted on a guide shaft. The guide shaft is pivoted so that an optical axis of an optical system becomes perpendicular to an optical disk. The holder is provided to be tilted in a radial plane with respect to the optical disk when the holder is moved for focusing the optical system.