Patents by Inventor Toshihiro Sekiguchi
Toshihiro Sekiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030132479Abstract: In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.Type: ApplicationFiled: January 3, 2003Publication date: July 17, 2003Inventors: Yoshitaka Nakamura, Masayoshi Hirasawa, Isamu Asano, Tsuyoshi Tamaru, Satoru Yamada, Keizo Kawakita, Toshihiro Sekiguchi, Yoshitaka Tadaki, Takuya Fukuda
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Patent number: 6593396Abstract: There is provided an adhesion type denture adhesive having superior cleanability, which can be easily removed from a denture base and an oral mucosa for cleansing after the use, while possessing a superior force for stabilizing a denture. The denture adhesive containing a water-soluble polymer as a main ingredient, and containing 0.5 to 60% by weight of an alginate and 0.1 to 20% by weight of calcium sulfate contained therein.Type: GrantFiled: June 8, 2001Date of Patent: July 15, 2003Assignee: Healthtech CorporationInventors: Hiroaki Muramatsu, Toshihiro Sekiguchi
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Patent number: 6555861Abstract: In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing the capacity for a word line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than that of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each space (contact holes) between the gate electrodes is set larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.Type: GrantFiled: January 22, 2001Date of Patent: April 29, 2003Assignee: Hitachi, Ltd.Inventors: Satoru Yamada, Kiyonori Oyu, Takafumi Tokunaga, Hiroyuki Enomoto, Toshihiro Sekiguchi
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Publication number: 20020192905Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.Type: ApplicationFiled: August 23, 2002Publication date: December 19, 2002Inventors: Toshihiro Sekiguchi, Yoshitaka Tadaki, Keizo Kawakita, Hideo Aoki, Toshikazu Kumai, Kazuhiko Saito, Michio Nishimura, Michio Tanaka, Katsuo Yuhara, Shinya Nishio, Toshiyuki Kaeriyama, Songsu Cho
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Publication number: 20020182798Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.Type: ApplicationFiled: May 31, 2002Publication date: December 5, 2002Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
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Patent number: 6480082Abstract: A circuit breaker having a safe construction, where no electrically charged portions are exposed in an accessory installation area or anywhere outside a main circuit case even if a cover of the circuit breaker is opened in a live condition. In order to achieve above object, the circuit breaker of this invention includes the main circuit case made of an insulating material, and an opening-closing trip mechanism disposed outside of the main circuit case and electrically insulated from the main circuit. According to this invention, a circuit breaker capable of eliminating the risk of an electric shock, thereby providing the excellent safety can be obtained.Type: GrantFiled: December 16, 1997Date of Patent: November 12, 2002Assignee: Hitachi, Ltd.Inventors: Kazuya Aihara, Terumi Shimano, Eietsu Sato, Yukihide Yamada, Koichi Yokoyama, Toru Ohshima, Hidetaka Fujita, Toshihiro Sekiguchi
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Patent number: 6461161Abstract: There is provided a tooth surface treatment method, which enables one to effectively inhibit the progress of dental caries without impairing the aesthetics. The tooth surface treatment method of the invention includes applying a solution comprising a silver compound in an affected part of a tooth and then applying a solution comprising at least one compound selected from the group of sodium chloride, sodium bromide, sodium iodide, potassium chloride, potassium bromide, potassium iodide, magnesium chloride, magnesium bromide, magnesium iodide, calcium chloride, calcium bromide, calcium iodide thereto.Type: GrantFiled: May 25, 2001Date of Patent: October 8, 2002Assignee: GC CorporationInventors: Hien Ngo, Geoffrey M. Knight, Graham George Craig, Toshihiro Sekiguchi
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Publication number: 20020127793Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.Type: ApplicationFiled: December 3, 2001Publication date: September 12, 2002Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Patent number: 6399438Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.Type: GrantFiled: April 9, 2001Date of Patent: June 4, 2002Assignee: Hitachi, Ltd.Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
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Publication number: 20020058727Abstract: There is provided a resin composition for soft relining material that can meet the performances required in a soft relining material for denture base, such as a proper softness and fitness between a denture base and an oral mucosa, without using a phthalate-based plasticizer widely used in the conventional art resin composition for soft relining material, which is pointed out to have a possibility for influencing living bodies as an endocrine disrupter. The soft resin composition for denture base is constructed of (a) a (meth)acrylate monomer having at least one unsaturated double bond; (b) an acid ester-based plasticizer; (c) a (meth)acrylate polymer or copolymer; and (d) a polymerization initiator.Type: ApplicationFiled: September 10, 2001Publication date: May 16, 2002Applicant: GC CorporationInventors: Mizuki Nakayama, Tomohiro Kumagai, Toshihiro Sekiguchi
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Publication number: 20020043680Abstract: Disclosed is a semiconductor integrated circuit device including a DRAM having fine memory cells and a reduced bit line capacity. A side wall insulating film of a gate electrode (word line) is constructed by a side wall insulating film made of silicon nitride and a side wall insulating film made of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing a capacity for a word line of a bit line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than the level of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each of spaces (contact holes) between the gate electrodes is set to be larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.Type: ApplicationFiled: January 22, 2001Publication date: April 18, 2002Inventors: Satoru Yamada, Kiyonori Oyu, Takafumi Tokunaga, Hiroyuki Enomoto, Toshihiro Sekiguchi
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Publication number: 20020028574Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected,, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.Type: ApplicationFiled: July 27, 2001Publication date: March 7, 2002Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Publication number: 20020013384Abstract: There is provided an adhesion type denture adhesive having superior cleanability, which can be easily removed from a denture base and an oral mucosa for cleansing after the use, while possessing a superior force for stabilizing a denture. The denture adhesive containing a water-soluble polymer as a main ingredient, and containing 0.5 to 60% by weight of an alginate and 0.1 to 20% by weight of calcium sulfate contained therein.Type: ApplicationFiled: June 8, 2001Publication date: January 31, 2002Applicant: HEALTHTECH CORPORATIONInventors: Hiroaki Muramatsu, Toshihiro Sekiguchi
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Publication number: 20010028082Abstract: In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.Type: ApplicationFiled: June 15, 2001Publication date: October 11, 2001Inventors: Yoshitaka Nakamura, Masayoshi Hirasawa, Isamu Asano, Tsuyoshi Tamaru, Satoru Yamada, Keizo Kawakita, Toshihiro Sekiguchi, Yoshitaka Tadaki, Takuya Fukuda
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Publication number: 20010023099Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.Type: ApplicationFiled: April 9, 2001Publication date: September 20, 2001Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
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Patent number: 6287912Abstract: A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.Type: GrantFiled: September 3, 1999Date of Patent: September 11, 2001Assignee: Hitachi, Ltd.Inventors: Hisao Asakura, Yoshitaka Tadaki, Toshihiro Sekiguchi, Ryo Nagai, Masafumi Miyamoto, Masayuki Nakamura
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Patent number: 6281071Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.Type: GrantFiled: May 25, 1999Date of Patent: August 28, 2001Assignee: Hiatchi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Patent number: 6258649Abstract: In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.Type: GrantFiled: September 3, 1999Date of Patent: July 10, 2001Assignee: Hitachi, LTDInventors: Yoshitaka Nakamura, Masayoshi Hirasawa, Isamu Asano, Tsuyoshi Tamaru, Satoru Yamada, Keizo Kawakita, Toshihiro Sekiguchi, Yoshitaka Tadaki, Takuya Fukuda
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Patent number: 6215144Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.Type: GrantFiled: January 25, 1999Date of Patent: April 10, 2001Assignee: Hitachi, Ltd.Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
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Patent number: 6198128Abstract: In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.Type: GrantFiled: September 7, 1999Date of Patent: March 6, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hisao Asakura, Yoshitaka Tadaki, Toshihiro Sekiguchi, Ryo Nagai, Masafumi Miyamoto, Masayuki Nakamura, Shinichi Miyatake, Tsuyuki Suzuki, Masahiro Hyoma