Patents by Inventor Toshihiro Sekiguchi
Toshihiro Sekiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6136881Abstract: A photocuring resin composition for orthodontics is disclosed, comprising:(a) 5.about.50% by weight of a urethane bond-free (meth)acrylate having an average molecular weight of 100.about.300 and having at least one unsaturated double bond;(b) 10.about.60% by weight of a urethane bond-containing (meth)acrylate having an average molecular weight of 300.about.5,000 and having at least one unsaturated double bond;(c) 5.about.30% by weight of a crosslinked polyurethane powder;(d) 10.about.50% by weight of an inorganic filler; and(e) 0.03.about.3% by weight of a photocuring initiator.Type: GrantFiled: September 3, 1998Date of Patent: October 24, 2000Assignee: GC CorporationInventors: Toshihiro Sekiguchi, Shunji Sugano
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Patent number: 6077735Abstract: A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.Type: GrantFiled: August 28, 1996Date of Patent: June 20, 2000Assignee: Texas Instruments IncorporatedInventors: Yuji Ezaki, Shinya Nishio, Fumiaki Saitoh, Hideo Nagasawa, Toshiyuki Kaeriyama, Songsu Cho, Hisao Asakura, Jun Murata, Yoshitaka Tadaki, Toshihiro Sekiguchi, Keizo Kawakita
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Patent number: 6060352Abstract: A method for fabricating DRAMs each having a COB structure, and the semiconductor device formed by this method, are provided. In one embodiment, the word line and/or bit line is covered with an insulating film having a comparatively small etching rate. Contact holes are formed while being defined by those insulating films in self-alignment.Type: GrantFiled: January 28, 1998Date of Patent: May 9, 2000Assignee: Hitachi, Ltd.Inventors: Toshihiro Sekiguchi, Hideo Aoki, Yoshitaka Tadaki, Keizo Kawakita, Jun Murata, Katsuo Yuhara, Michio Nishimura, Kazuhiko Saitoh, Minoru Ohtsuka, Masayuki Yasuda, Toshiyuki Kaeriyama, Songsu Cho
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Patent number: 6023084Abstract: A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.Type: GrantFiled: October 19, 1998Date of Patent: February 8, 2000Assignees: Hitachi, Ltd., Texas Instruments Inc.Inventors: Yoshitaka Tadaki, Jun Murata, Toshihiro Sekiguchi, Hideo Aoki, Keizo Kawakita, Hiroyuki Uchiyama, Michio Nishimura, Michio Tanaka, Yuji Ezaki, Kazuhiko Saitoh, Katsuo Yuhara, Songsu Cho
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Patent number: 5937290Abstract: In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.Type: GrantFiled: May 27, 1997Date of Patent: August 10, 1999Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Toshihiro Sekiguchi, Yoshitaka Tadaki, Keizo Kawakita, Katsuo Yuhara, Kazuhiko Saito, Shinya Nishio, Michio Tanaka, Michio Nishimura, Toshiyuki Kaeriyama, Songsu Cho
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Patent number: 5933726Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.Type: GrantFiled: August 27, 1996Date of Patent: August 3, 1999Assignee: Texas Instruments IncorporatedInventors: Michio Nishimura, Kazuhiko Saitoh, Masayuki Yasuda, Takashi Hayakawa, Michio Tanaka, Yuji Ezaki, Katsuo Yuhara, Minoru Ohtsuka, Toshikazu Kumai, Songsu Cho, Toshiyuki Kaeriyama, Keizo Kawakita, Toshihiro Sekiguchi, Yoshitaka Tadaki, Jun Murata, Hideo Aoki, Akihiko Konno, Kiyomi Katsuyama, Takafumi Tokunaga, Yoshimi Torii
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Patent number: 5933724Abstract: A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.Type: GrantFiled: August 26, 1996Date of Patent: August 3, 1999Assignees: Hitachi, Ltd., Texas InstrumentsInventors: Toshihiro Sekiguchi, Yoshitaka Tadaki, Keizo Kawakita, Jun Murata, Katsuo Yuhara, Toshikazu Kumai, Michio Tanaka, Michio Nishimura, Kazuhiko Saitoh, Takatoshi Kakizaki, Takeshi Sakai, Toshiyuki Kaeriyama, Songsu Cho
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Patent number: 5930624Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry.Type: GrantFiled: January 26, 1998Date of Patent: July 27, 1999Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Patent number: 5917211Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.Type: GrantFiled: November 25, 1997Date of Patent: June 29, 1999Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
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Patent number: 5831300Abstract: A semiconductor memory device has a semiconductor substrate, word line conductors and bit line conductors, and memory cells provided at intersections between the word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.Type: GrantFiled: October 16, 1996Date of Patent: November 3, 1998Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Yoshitaka Tadaki, Jun Murata, Toshihiro Sekiguchi, Hideo Aoki, Keizo Kawakita, Hiroyuki Uchiyama, Michio Nishimura, Michio Tanaka, Yuji Ezaki, Kazuhiko Saitoh, Katsuo Yuhara, Songsu Cho
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Patent number: 5804479Abstract: The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array.Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.Type: GrantFiled: August 9, 1996Date of Patent: September 8, 1998Assignees: Hitachi, Ltd., Texas Instruments Inc.Inventors: Hideo Aoki, Jun Murata, Yoshitaka Tadaki, Toshihiro Sekiguchi, Keizo Kawakita, Takashi Hayakawa, Katsutoshi Matsunaga, Kazuhiko Saitoh, Michio Nishimura, Minoru Ohtsuka, Katsuo Yuhara, Michio Tanaka, Yuji Ezaki, Toshiyuki Kaeriyama, SongSu Cho
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Patent number: 5753550Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry.Type: GrantFiled: March 25, 1996Date of Patent: May 19, 1998Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Patent number: 5734188Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.Type: GrantFiled: July 1, 1996Date of Patent: March 31, 1998Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
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Patent number: 5629898Abstract: A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.Type: GrantFiled: February 29, 1996Date of Patent: May 13, 1997Assignee: Hitachi, Ltd.Inventors: Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Katsuyuki Sato, Hidetoshi Iwai, Makoto Saeki, Jun Murata, Yoshitaka Tadaki, Toshihiro Sekiguchi, Osamu Tsuchiya
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Patent number: 5578849Abstract: A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.Type: GrantFiled: November 16, 1994Date of Patent: November 26, 1996Assignees: Hitachi, Ltd., Texas Instruments, Inc.Inventors: Yoshitaka Tadaki, Jun Murata, Toshihiro Sekiguchi, Hideo Aoki, Keizo Kawakita, Hiroyuki Uchiyama, Michio Nishimura, Michio Tanaka, Yuji Ezaki, Kazuhiko Saitoh, Katsuo Yuhara, Songsu Cho
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Patent number: 5504029Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure.Type: GrantFiled: June 6, 1994Date of Patent: April 2, 1996Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Patent number: 5357426Abstract: A party production apparatus allows a party program to be stored in advance and automatically serves various dishes in accordance with the progress of the party to produce the party successfully. The party production apparatus comprises a kitchen counter, a table counter, and a controller. The kitchen counter includes cooking device. The table counter includes a frame, a table provided on the frame, a food displaying section formed on the table, a storage chamber provided in the frame for accommodating a plurality of dishes therein, and a transport apparatus for transporting a selected dish or dishes accommodated in the storage chamber to the food displaying section. The controller includes a register for storing therein a party program including a plurality of operations to be executed successively in a time series relationship and controls the transport apparatus in accordance with an order sequence stored in the register to transport the dish or dishes to the food displaying section.Type: GrantFiled: February 1, 1993Date of Patent: October 18, 1994Assignee: Sanyo Electric Co., Ltd.Inventors: Minoru Morita, Mitsumasa Kumagai, Toshihiro Sekiguchi
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Patent number: 5349218Abstract: A semiconductor integrated circuit device has a semiconductor memory cell array including word lines, data lines and a plurality of memory cells provided at cross points of the word and data lines. Each memory cell has a cell selection transistor and an information storage capacitor connected in series. The cell selection transistor in one cell includes first and second doped regions formed in a main surface of a semiconductor substrate, a first insulating film formed on the main surface between the first and second doped regions and a control electrode layer formed on the first insulating film between the first and second doped regions. The first doped region is connected with a data line, while the control electrode is connected with a word line.Type: GrantFiled: April 29, 1992Date of Patent: September 20, 1994Assignees: Hitachi, Ltd., Texas Instruments Japan, Inc.Inventors: Yoshitaka Tadaki, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Toru Kaga, Jun Murata, Osaomi Enomoto
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Patent number: 5264712Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.Type: GrantFiled: May 7, 1992Date of Patent: November 23, 1993Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
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Patent number: 5153685Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.Type: GrantFiled: September 19, 1988Date of Patent: October 6, 1992Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi