Abstract: A liquid discharge system including a piezoelectric element that is displaced in accordance with a drive signal and discharges liquid; a drive signal output circuit that outputs the drive signal; a measurement circuit that measures a first capacitance of the piezoelectric element; and a determination circuit that determines a deterioration state of the piezoelectric element based on the first capacitance.

Abstract: A current detection circuit includes an operational amplifier, a current sense amplifier including a first resistor and a second resistor, and a level shifter. The first resistor is provided between one end of a shunt resistor and a first input node of the operational amplifier. The second resistor is provided between the other end of the shunt resistor and a second input node of the operational amplifier. The level shifter controls voltages of the first input node and the second input node by controlling, according to a voltage at the one end of the shunt resistor, currents supplied to the first input node and the second input node.

Abstract: A current detection circuit includes an operational amplifier, a current sense amplifier including a first resistor and a second resistor, and a level shifter. The first resistor is provided between one end of a shunt resistor and a first input node of the operational amplifier. The second resistor is provided between the other end of the shunt resistor and a second input node of the operational amplifier. The level shifter controls voltages of the first input node and the second input node by controlling, according to a voltage at the one end of the shunt resistor, currents supplied to the first input node and the second input node.

Abstract: A circuit device includes: a first physical layer circuit to which a first bus compliant with a USB standard is connected; a second physical layer circuit to which a second bus compliant with the USB standard is connected; a processing circuit that performs transfer processing in which a packet received from the first bus via the first physical layer circuit is transferred to the second bus via the second physical layer circuit, and a packet received from the second bus via the second physical layer circuit is transferred to the first bus via the first physical layer circuit; a bus monitor circuit that performs a monitor operation with respect to the first and second buses; and a bus switch circuit that switches on or off a connection between the first bus and the second bus based on a monitor result from the bus monitor circuit.

Abstract: A circuit device includes a packet output circuit configured to amplify a current for a packet and output the packet to a USB-compliant bus, a detection circuit configured to detect whether an amplitude level of the packet transmitted to the bus has exceeded a disconnection detection level for a prescribed time period, a determination circuit configured to set a current for an EOP of an SOF packet output by the packet output circuit to lower than a current for a section other than the EOP, and when it is detected, by the detection circuit, that an amplitude level of the EOP has exceeded the disconnection detection level, determine that a device that was connected to the bus is disconnected.

Abstract: A circuit device includes a physical layer circuit coupled to a data bus, and a processing circuit that controls the physical layer circuit and performs communications processing through the data bus. The processing circuit operates with a voltage supplied from a ground line as a power supply voltage VSS on a low potential side, and the physical layer circuit operates based on a power supply voltage VSSA on the low potential side supplied from a power supply line not coupled to the ground line in the circuit device, and a power supply voltage HVDDA on a high potential side set with reference to the power supply voltage VSSA.

Abstract: A circuit device includes a control circuit configured to instruct, when a detection circuit detects that an amplitude level of a packet exceeds a disconnecting detection level, a packet output circuit to lower an amplitude level of a part or all of packets, and after the instruction, to determine that, when the detection circuit detects that an amplitude level of a packet again exceeds the disconnecting detection level, a USB device connected to a bus is disconnected.

Abstract: Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.

Abstract: A circuit device includes a packet output circuit configured to amplify a current for a packet and output the packet to a USB-compliant bus, a detection circuit configured to detect whether an amplitude level of the packet transmitted to the bus has exceeded a disconnection detection level for a prescribed time period, a determination circuit configured to set a current for an EOP of an SOF packet output by the packet output circuit to lower than a current for a section other than the EOP, and when it is detected, by the detection circuit, that an amplitude level of the EOP has exceeded the disconnection detection level, determine that a device that was connected to the bus is disconnected.

Abstract: A circuit device includes a control circuit configured to instruct, when a detection circuit detects that an amplitude level of a packet exceeds a disconnecting detection level, a packet output circuit to lower an amplitude level of a part or all of packets, and after the instruction, to determine that, when the detection circuit detects that an amplitude level of a packet again exceeds the disconnecting detection level, a USB device connected to a bus is disconnected.

Abstract: Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.

Abstract: A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard on in a first period and off in a second period, and a processing circuit that performs, in the second period, packet transfer processing on a transfer route that includes the first bus, the first and second physical layer circuits, the second bus. The bus switch circuit includes a first switch circuit, a second switch circuit, and a signal line connected between the first switch circuit and the second switch circuit.

Abstract: This driving circuit includes a data line driving circuit that supplies a gray-scale signal to a plurality of data lines, a regulator that stabilizes a supplied power supply voltage and supplies the stabilized power supply voltage to a smoothing capacitor and the data line driving circuit, a switching circuit that switches the connection state of a plurality of circuit elements that constitute the regulator, and a control circuit that controls the switching circuit. The control circuit controls the switching circuit so as to set voltage stabilization capability of the regulator to a predetermined level when the gray-scale signal is supplied to pixel elements, and controls the switching circuit so as to set the voltage stabilization capability of the regulator to a level lower than the predetermined level or to stop an operation of the regulator, when the gray-scale signal is not supplied to the pixel elements.

Abstract: A circuit device includes a physical layer circuit coupled to a data bus, and a processing circuit that controls the physical layer circuit and performs communications processing through the data bus. The processing circuit operates with a voltage supplied from a ground line as a power supply voltage VSS on a low potential side, and the physical layer circuit operates based on a power supply voltage VSSA on the low potential side supplied from a power supply line not coupled to the ground line in the circuit device, and a power supply voltage HVDDA on a high potential side set with reference to the power supply voltage VSSA.

Abstract: A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard, on in a first period and off in a second period, and a processing circuit that performs, in the second period, processing for transferring packets on a transfer route that includes the first bus, the first and second physical layer circuits, and the second bus. When a host chirp K/J is detected on the first bus by the first physical layer circuit, the second physical layer circuit outputs a host chirp K/J to the second bus in the state where connection between the first bus and the second bus is switched off by the bus switch circuit.

Abstract: A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard on in a first period and off in a second period, and a processing circuit that performs, in the second period, packet transfer processing on a transfer route that includes the first bus, the first and second physical layer circuits, the second bus. The bus switch circuit includes a first switch circuit, a second switch circuit, and a signal line connected between the first switch circuit and the second switch circuit.

Abstract: A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard, on in a first period and off in a second period, and a processing circuit that performs, in the second period, processing for transferring packets on a transfer route that includes the first bus, the first and second physical layer circuits, and the second bus. When a host chirp K/J is detected on the first bus by the first physical layer circuit, the second physical layer circuit outputs a host chirp K/J to the second bus in the state where connection between the first bus and the second bus is switched off by the bus switch circuit.

Abstract: A transmission circuit includes a current output circuit that outputs a current to a first node, a first switch element provided between the first node and a first signal line, and a second switch element provided between the first node and a second signal line. When a transmission signal is at a first logic level, the first switch element is ON and the second switch element is OFF. When the transmission signal is at a second logic level, the first switch element is OFF and the second switch element is ON. The current output circuit outputs a second current in an n-bit period after the logic level of the transmission signal is inverted, and outputs a first current after the n-bit period.

Abstract: A circuit device includes: a transmitting circuit that performs transmission of a signal by current-driving signal lines in a transmission period; a receiving circuit that receives a signal that a transmitting circuit of a communication partner has transmitted by current-driving the signal lines, in a reception period that is different from the transmission period; and terminating resistor circuits that can be connected to the signal lines, and whose resistance value in the transmission period is set to a value that is smaller than a resistance value in the reception period.

Abstract: A transmission circuit includes a current output circuit that outputs a current to a first node, a first switch element provided between the first node and a first signal line, and a second switch element provided between the first node and a second signal line. When a transmission signal is at a first logic level, the first switch element is ON and the second switch element is OFF. When the transmission signal is at a second logic level, the first switch element is OFF and the second switch element is ON. The current output circuit outputs a second current in an n-bit period after the logic level of the transmission signal is inverted, and outputs a first current after the n-bit period.