Abstract: An opaque defect is processed by scanning with a high load or height fixed mode using a probe harder than a pattern material of a photomask at the time of going scanning, and is observed by scanning with a low load or intermittent contact mode at the time of returning scanning so as to detect an ending point of the opaque defect by the height information. When there is a portion reaching to a glass substrate as an ending point, this portion is not scanned by the high load or height fixed mode in the next processing, and only a portion not reaching to the ending point is scanned by the high load or height fixed mode.

Abstract: A network routing device according to the invention transmits a packet via a second port based upon destination information included in the packet received via a first port referring to a routing table. In addition, the network routing device calculates beforehand a third port which is a transfer destination when a fault occurs in a destination connected to the second port. Further, the network routing device holds scenario information including a combination of the second port and the third port and updates the routing table based upon the scenario information when a fault is detected in either of the ports.

Abstract: There is provided a network connection apparatus including a plurality of line connection parts 201 connected to network lines 111 to transmit and receive packets, a transmission destination decision part 104 for deciding a transmission destination on the basis of header information of packet received by a first one of the plurality of line connection parts, a packet transfer part 103 for transferring packets to a second line connection destination corresponding to the transmission destination decided by the transmission destination decision part, a power supply part 102 for supplying power to the line connection parts and a power control part 203 for controlling supply of power to each of the line connection parts from the power supply part.

Abstract: A network system has a first LAN, a second LAN, and a storage device for storing data accessible from the first LAN and the second LAN. A control apparatus controls accessibility of the data stored in the storage device from the first LAN and the second LAN. The control apparatus includes an access prevention device for preventing access from the first LAN to the second LAN and from the second LAN to the first LAN and a device for overriding a setting of the access prevention device to allow accessibility of the second LAN from the first LAN.

Abstract: An object of the present invention is to provide pharmaceutical compositions for inhibiting mesangial cell proliferation or mesangial matrix production without causing hypercalcemia. According to the present invention, therapeutic agents for glomerulosclerosis containing 1?,3?-dihydroxy-20?-(3-hydroxy-3-methylbutyloxy)-9,10-seco-5,7,10 (19)-pregnatriene as an active ingredient are provided.

Abstract: An object of the present invention is to provide pharmaceutical compositions for inhibiting mesangial cell proliferation or mesangial matrix production without causing hypercalcemia.

Abstract: An object of the present invention is to provide pharmaceutical compositions for inhibiting mesangial cell proliferation or mesangial matrix production without causing hypercalcemia. According to the present invention, therapeutic agents for glomerulosclerosis containing 1&agr;,3&bgr;-dihydroxy-20&agr;-(3-hydroxy-3-methylbutyloxy)-9,10-seco-5,7,10 (19)-pregnatriene as an active ingredient are provided.

Abstract: A focused ion beam machining method for etching the surface of a sample to obtain a desired profile formation portion by recurrently irradiating a focused ion beam to a desired region of the sample, wherein the recurrently scanned region is enlarged with the elapse of time during the etching and scanning of the sample with the focused ion beam is performed in parallel with the profile formation portion, and the profile formation portion is scanned after all other portions of the recurrently scanned region have been scanned.

Abstract: To provide a focused ion beam optical axis alignment method and a focused ion beam apparatus which make axis alignment work of for example when replacing an ion source of a focused ion beam apparatus easy.

Abstract: An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

Abstract: A photograph collating system for combining and collating negative films and prints. The system includes a conveyer mechanism (70) extending through a negative film intake station (71) for receiving the negative films from a negative film outlet (60), a print intake station (73) for receiving the prints from a print outlet (50), and a collating station (74) for collating the negative films and prints.The conveyer mechanism (70) includes trays (100) for transporting the negative films (2) and the prints (3), a guide circuit (80) defining a transport passage of the trays, and a drive device (90) for moving the trays along the guide circuit (80). Each of the trays having moved to the collating station (74) is disengaged from the drive device by contact with a preceding one of the trays in a direction of transport.

Abstract: The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

Abstract: A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin.

Abstract: The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

Abstract: A photographic printing apparatus includes a sorting apparatus comprising a plurality of receptacles for receiving negative films and prints which circulate in a closed loop path between a film loading station in close proximity to an exposure apparatus and a print loading station where prints, cut from a continuous web of photographic paper, are delivered. The receptacles are driven such that each receptacle related to a receptacle loaded with a specific negative film at the film loading station is positioned in the print loading station in time before a cluster of prints made from the specific negative film is delivered from the photographic printing apparatus.

Abstract: A data processor being provided with a microdecoder which decodes instruction codes comprising two operation code parts, a source operand specifying part and a destination operand specifying part, wherein an optional bit area of source data (a register of a general register file or a memory) is inserted in an optional bit area (determined by the value of the first operation code part) of a destination register according to the decoding result, and an optional bit area (determined by the value of the second operation code part) of a source register is extracted and stored in an optional bit area of destination (a register of the general register file or the memory), thereby making it possible to "process the insertion and extraction operations to and from optional byte positions of registers" at a high speed with short instruction code size.

Abstract: A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.

Abstract: A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries.

Abstract: A processor according to the present invention includes a user-accessible 1 bit register for indicating, upon instruction breaking or data breaking occurring, whether any instruction or data to be debugged is existent in a cache memory or in a memory, and the 1 bit register possesses a bit issued correspondingly to a hit signal issued from the cache memory, whereby it can be known with each whether the instruction or data is existent in the cache memory or in the memory.

Abstract: A data cache, for use in a memory having an address space including tag addresses for identifying blocks of storage locations and a set of select addresses for identifying storage locations in a block, includes a set select decoder that decodes only a subset of said set of select addresses that identify sub-blocks of storage locations located at the upper and lower boundaries of a block. Thus, data in storage locations accessed by addresses near block boundaries which have a high number of bit transitions is registered to the cache so that the high number of bit transitions does not have to be driven on an external bus so that noise is reduced.