Abstract: A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries.

Abstract: In order to reduce the capacity of a character ROM without reducing the character information, n-bit bit pattern data and sequence data having information necessary for composing n-bit m components are stored in first memory means (character ROM). Second memory means has addresses corresponding to each display position on the screen and holds addresses for the first memory means as a data. In accordance with the address from the second memory means and the sequence data from the first memory means, address modifying means produces an address of a scanning line with respect to pertinent character for the first memory means. According to this address, the bit pattern data is read out from the first memory means.

Abstract: A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries.

Abstract: A semiconductor integrated circuit device is provided which include a plurality of cell columns each having a number of unit cells previously fabricated on a semiconductor substrate selected from the plural kinds of unit cells which are formed in desired circuits by electrically connecting circuit devices previously arranged. Each column includes at least one kind of unit cell of a dynamic circuit which has a node in a floating state during the operation of the cell unit. A fixed potential shield layer is also provided on the cell columns so as to cover the nodes of the dynamic circuits. By virtue of this, a wiring area for electrically connecting the desired cell units can be located between the cell columns and above the shield layer. In other words, signal wirings in the wiring area can pass over the nodes of the dynamic circuits. without adverse parasitic effects. The unit cell can also be provided with a precharge circuit comprising a standard cell and an in-cell wiring layer.

Abstract: An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

Abstract: This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted.

Abstract: A dynamic semiconductor logic circuit comprising a MOS FET logic section for effecting a high-speed logic operation in response to input logic signals after precharging of an output mode and internal nodes the logic section, a CMOS/BiCMOS output buffer section for outputting a result of the logic operation, and a noise suppression section for preventing erroneous operations without sacrificing the high-speed operation characteristic. The circuit, which is fabricated with 0.5-.mu.m-rule technology and operates at high speed with a low-voltage power source of 4.5 V or less, has a precharging section for precharging the output node and internal nodes of the MOS FET logic section and a noise suppression section for latching the output node of the logic section to the source potential by feeding back the output of an output buffer section in order to enlarge the soft error margin. The latching current is held at less than a predetermined ratio to maintain the high-speed operation characteristic.

Abstract: A semiconductor integrated circuit device is provided which includes a logic circuit utilizing an error detection code.

Abstract: An output signal of a logic portion is inputted to the gate of FET inside an output buffer portion to inverse the signal polarity by this FET and is outputted through a bipolar transistor effecting an emitter follower operation or the like. An FET controlled by a clock signal is disposed between the base of the bipolar transistor and the ground and an FET which is turned ON during a pre-charge operation and when the bipolar transistor is OFF during logic calculation is disposed between the emitter and the ground so as to short-circuit the emitter and the ground during the pre-charge operation. In this manner, higher operation speed, higher integration density and high operation margin can be accomplished without losing the characteristic features of a Bi-CMOS dynamic logic circuit in its high operation speed and low power dissipation.

Abstract: In a recording tape cartridge having a cartridge case, magnetic recording tape and a front lid and a rear lid for protecting the magnetic tape, there are provided entrance preventing members at a bottom the cartridge case facing to clearances between side edges of the front lid and case body for preventing entrance of harmful floating particles into the area near the recording tape so as to prevent corrosion of the recording tape.

Abstract: An output interface circuit comprises a CMOS circuit including a pair of complementary MOS transistors and receiving an input signal at the gates of the paired MOS transistors, a bipolar transistor having its base connected to the output of the CMOS circuit and its emitter from which an output signal is delivered, and a control circuit connected between the paired MOS transistors and operable, upon the fall of the output signal, to cut off a current flowing through any one of the paired MOS transistors so as to control the low level at the output of the CMOS circuit such that the low level does not fall before a potential level by which the low level of the output signal is permitted to be at a desirable predetermined potential level. Specifically, the CMOS circuit includes a pair of complementary MOS transistors comprised of a P-type MOS transistor and an N-type MOS transistor and receives an input signal of CMOS level to operate in inverter fashion.

Abstract: The present cathode for cathode ray tube of directly heating type is characterized by comprising a cathode substrate body having two leg pieces extended in the same direction and a flat part connected to one end of each leg piece, prepared by shaping a flat metal plate of nickel- or cobalt-based alloy, a bonding layer having an uneven surface prepared by diffusion bonding by heating a powder layer comprising powders of alloy or mixture of nickel and cobalt formed on the flat part, to which a thermionic emission layer is to be bonded, and the thermionic emission layer, and has a very small deformation when used and a longer life.A cathode with much less deformation and much longer life can be obtained by using a cathode substrate body prepared from a flat metal plate provided with a thinner metal layer of at least one of nickel and cobalt on its surface than the flat metal plate by diffusion bonding.

Abstract: In a process for producing a cathode for a cathode ray tube of directly heating type, which comprises shaping a heat-resistant and electro-conductive, flat metal plate, into a cathode substrate body having two leg pieces extended in the same direction and a flat part connected to one end of each leg piece, forming a heat-diffusible metal powder layer having a good affinity to said flat metal plate and on an outer surface of said flat part, heating the powder layer, thereby diffusion bonding the powder layer to the flat part and forming a bonding layer having an uneven surface, to which a thermionic emission layer is to be bonded, and forming the thermionic emission layer on the surface of the bonding layer, the process is characterized by forming on said flat metal plate a metal layer having a good affinity to the flat metal plate, by diffusion bonding, thereby forming a compound plate, and shaping the resulting compound plate into the shape of said cathode substrate body.