Abstract: The high-strength steel sheet includes, by mass %: C: 0.01% to 0.10%; Si: 0.15% or less; Mn: 0.80% to 1.80%; P: 0.10% or less; S: 0.015% or less; Al: 0.10% to 0.80%; Cr: 0.01% to 1.50%; N: 0.0100% or less; and a balance consisting of iron and inevitable impurities, in which a metallic structure is composed of ferrite and a hard second phase, the area fraction of the ferrite is 80% or more, the area fraction of the hard second phase is 1% to 20%, the fraction of unrecrystallized ferrite in the ferrite is less than 10%, the ferrite grain sizes are 5 ?m to 20 ?m, and the fraction of the ferrite crystal grains having an aspect ratio of 1.2 or less in the entire ferrite crystal grains is 60% or more.

Abstract: A two-part foam hair dye having a first agent containing an alkali agent, a second agent containing hydrogen peroxide, and a non-aerosol foamer container, wherein the first agent contains (A), from 0.20 to 2.00 mol/kg of (B), and 0.05 mol/kg or greater of (C1); a total concentration of (C1) and (C2) in the first agent is from 0.16 to 0.50 mol/kg: and a mixture of the first agent and the second agent has a viscosity of from 1 to 300 mPa·s; (A) a water-soluble cationic polymer, (B) an alkali metal ion, (C1) an oxidation dye having a phenolic hydroxyl group, and (C2) an anionic surfactant.

Abstract: A logical circuit device comprises a plurality of logical blocks including reconfigurable logical configurations and a network including reconfigurable connections among the plurality of logical blocks, wherein at least one of the plurality of logical blocks comprises a basic logical operation element. The basic logical operation element receives a first data signal and a first validity indication signal that becomes an asserted state when the first data signal is valid, outputs a second data signal generated by a first logical operation based on the first data signal and a second validity indication signal that becomes an asserted state when the second data signal is valid, and sets the second data signal to the asserted state in response to the asserted state of the first validity indication signal.

Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.

Abstract: A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.

Abstract: A two-part foam hair dye having a first agent containing an alkali agent, a second agent containing hydrogen peroxide, and a non-aerosol foamer container, wherein the first agent contains (A), from 0.20 to 2.00 mol/kg of (B), and 0.05 mol/kg or greater of (C1); a total concentration of (C1) and (C2) in the first agent is from 0.16 to 0.50 mol/kg: and a mixture of the first agent and the second agent has a viscosity of from 1 to 300 mPa·s; (A) a water-soluble cationic polymer, (B) an alkali metal ion, (C1) an oxidation dye having a phenolic hydroxyl group, and (C2) an anionic surfactant.

Abstract: A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.

Abstract: A semiconductor integrated circuit includes a plurality of flip-flop sets, and a logic circuit configured to consolidate error-detection signals output from the flip-flop sets into one output signal, wherein each of the flip-flop sets includes one or more flip-flops configured to latch input data in synchronization with a common clock signal, and an error detection-&-correction circuit configured to detect and correct an error in data stored in the flip-flops, and to produce one of the error-detection signals indicative of the detection of the error upon the detection of the error.

Abstract: A method of designing a semiconductor integrated circuit includes defining a tolerable range in which an operating temperature and an operating power supply voltage of a semiconductor integrated circuit are allowed to vary, computing a target temperature and a target power supply voltage that cancel variation in circuit characteristics caused by process variation of the semiconductor integrated circuit, separately for each circuit characteristic responsive to the process variation, and designing the semiconductor integrated circuit such that the semiconductor integrated circuit properly operates with any temperature and power supply voltage within the tolerable range based on an assumption that the semiconductor integrated circuit is to operate within the tolerable range centered substantially at the target temperature and target power supply voltage.

Abstract: A logical circuit device comprises a plurality of logical blocks including reconfigurable logical configurations and a network including reconfigurable connections among the plurality of logical blocks, wherein at least one of the plurality of logical blocks comprises a basic logical operation element. The basic logical operation element receives a first data signal and a first validity indication signal that becomes an asserted state when the first data signal is valid, outputs a second data signal generated by a first logical operation based on the first data signal and a second validity indication signal that becomes an asserted state when the second data signal is valid, and sets the second data signal to the asserted state in response to the asserted state of the first validity indication signal.

Abstract: A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.

Abstract: A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.

Abstract: Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.

Abstract: A circuit board includes a substrate having a thickness in a first direction, extending in a plane perpendicular to the first direction, and having at least one of a through hole and a recess, and an optical transmission channel having an end thereof at a perimeter of the one of a through hole and a recess and having a portion thereof extending a predetermined distance from the end in a direction substantially perpendicular to the first direction, the portion being provided in the substrate or on a surface of the substrate.

Abstract: A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.

Abstract: A semiconductor integrated circuit includes a plurality of flip-flop sets, and a logic circuit configured to consolidate error-detection signals output from the flip-flop sets into one output signal, wherein each of the flip-flop sets includes one or more flip-flops configured to latch input data in synchronization with a common clock signal, and an error detection-&-correction circuit configured to detect and correct an error in data stored in the flip-flops, and to produce one of the error-detection signals indicative of the detection of the error upon the detection of the error.

Abstract: A method of designing a semiconductor integrated circuit includes defining a tolerable range in which an operating temperature and an operating power supply voltage of a semiconductor integrated circuit are allowed to vary, computing a target temperature and a target power supply voltage that cancel variation in circuit characteristics caused by process variation of the semiconductor integrated circuit, separately for each circuit characteristic responsive to the process variation, and designing the semiconductor integrated circuit such that the semiconductor integrated circuit properly operates with any temperature and power supply voltage within the tolerable range based on an assumption that the semiconductor integrated circuit is to operate within the tolerable range centered substantially at the target temperature and target power supply voltage.

Abstract: A semiconductor device includes one or more margin detecting circuits, each of which includes a first flip-flop having a first clock signal input node coupled to a clock supply node and a first data input node coupled to a data supply node, a second flip-flop having a second clock signal input node coupled to the clock supply node and a second data input node coupled to the data supply node, a delay element situated between the clock supply node and the second clock input node or between the data supply node and the second data input node, and a check circuit configured to check whether data stored in the first flip-flop matches data stored in the second flip-flop.

Abstract: A semiconductor integrated circuit includes a measurement circuit configured to detect a measuring quantity dependent on temperature, and a heating circuit configured to generate heat in response to a detection, by the measurement circuit, of the measuring quantity indicating that the temperature is lower than a predetermined level.

Abstract: An exhaust gas purification apparatus for use in an internal combustion engine comprises an exhaust gas duct connected to the engine through which exhaust gas containing NOx gas passes, and a catalyst disposed in the exhaust gas duct such that it contacts the exhaust gas. The catalyst chemically adsorbs NOx when a stoichiometric amount of a gaseous oxidizing agent present in the exhaust gas is larger than that of a gaseous reducing agent present in the exhaust gas for reducing NOx, adsorbed NOx is catalytically reduced in the presence of a reducing agent when the stoichiometric amount of the oxidizing agent is not larger that of the reducing agent.