Abstract: An LSI semiconductor device having a device isolation structure and a method of fabricating the isolation structure are presented. The device is a buried-type field-shielding device which is fabricated in non-active regions of the LSI circuit, and includes field-shield insulator film formed on the interior walls of trench cavities formed on the substrate and the field-shield electrodes buried within the trench cavity. Unlike the conventional buried-type isolation devices, the top surface of present isolation structure is level with the upper surface of the substrate. Therefore, this device structure utilizes the interior space of the substrate rather than the surface area of the substrate as in the conventional field-shield isolation structure.

Abstract: Four I/O pads are allocated to a group from one end to the other. A test circuit is provided for each of the groups. The four I/O pads are only connected to a test data terminal of an IC tester while the rest of the I/O pads are not connected. The test circuit comprises: a test mode detection circuit for detecting the device shifting to the test mode; a test mode writing circuit for writing data inputted from one of the I/O pads into four memory cells; a coincidence circuit for determining whether the data read from the four memory cells coincide with each other; and a data output circuit for outputting the result to the I/O pad.

Abstract: A press die set includes a hollow cylindrical guide bush mounted on a punch holder, a cylindrical retainer received within the guide bush, and a columnar guide post vertically mounted on a die holder and received within the retainer. First right angle grooves are formed on the outer surface of the guide post parallel to a longitudinal axis of the guide post. First planar surfaces are formed on an outer surface of the guide post parallel to the longitudinal axis of the guide post and perpendicular to a radius of the guide post. Second right angle grooves are formed on the inner surface of the guide bush parallel to a longitudinal axis of the guide bush. Second planar surfaces are formed on the inner surface of the guide bush parallel to the longitudinal axis of the guide bush and perpendicular to a radius of the guide bush. Cross roller bearings are positioned between the first and second right angle grooves, and plain roller bearings are positioned between the first and second planar surfaces.

Abstract: The bottoms 225 of circumferential groove 22 are equidistant from the axis of rotation 215 and constitute the sides of the column, the axes of rotation of which are common. The sides 226 and 227 of the circumferential groove 22 are not normal to the axis of rotation 215, and are beveled to form an acute angle to the bottom 225. That is, the sides 226 and 227 of the circumferential groove 22 form sides of cones the axes of rotation of which are common. The width of the circumferential groove 22 becomes widened from the surface to the inside. Resin 26 is coated on the surface of the circumferential groove 22 in such a manner that the coated surface has a substantially constant width. In this embodiment, a nylon type resin is coated with little peeling-off during use of the roller.

Abstract: Power protection circuitry comprising a first capacitor directly connected between a supply voltage line and a reference voltage line (ground line); a pair of MOS transistors cascade connected between the supply voltage line and the reference voltage line; and a second capacitor and a resistor (a CR circuit) connected in series between the supply voltage line and the reference voltage line. Part of abnormal, high frequency voltage resulting from static electricity applied to the supply voltage line is discharged via the first capacitor. The rest of the applied high frequency voltage, which the first capacitor fails to absorb, is discharged into the reference voltage line via the channels of the pair of MOS transistors turning on with a turn-on voltage supplied by a turn-on voltage supply circuit (the CR circuit) comprising the second capacitor and the resistor.

Abstract: An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.

Abstract: A semiconductor memory device includes a dielectric layer formed on a conductive thin film layer constituting a shield electrode for effecting element separation in a field area, the dielectric layer connected to a dielectric layer of a capacitor with a lower electrode having part thereof opposite to part of the shield electrode through the dielectric layer, and has an increase in electrode area of a memory cell to be able to attain the high level of integration.

Abstract: A method of writing or reading at least three different data in each memory cell, in a non-volatile semiconductor memory device having a plurality of memory cells, each memory cell having floating gate for setting a given threshold voltage in the memory cell. In addition, a non-volatile semiconductor memory device capable of checking if the data stored in the selected memory cell is correct by using one of at least two binary bits of the data as a parity bit, and a method of writing or reading data in or from that memory device.

Abstract: A MOS semiconductor device and a method of making the same are arranged to include a semiconductor substrate of a first conductivity type; a pair of impurity diffused layers of a second conductivity type different from the first conductivity type formed in the semiconductor substrate and mutually separated by a distance of 0.1 .mu.m or less; a gate insulating film including at least two layers of a silicon oxide film and a silicon nitride film and formed on a portion of the semiconductor substrate disposed between the pair of impurity diffused layers; and a gate electrode formed on the gate insulating film, wherein preferably the silicon nitride film has a thickness of 4.5 nm to 14.86 nm.

Abstract: A non-volatile semiconductor memory device capable of selectively storing one of at least three different data comprises a memory array including a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source, a circuit for producing a stepped voltage whose level is varied stepwise to a number of different levels corresponding to a number of data to be stored, a circuit for producing a pulse voltage having a predetermined voltage level and a predetermined pulse width, and a circuit for selecting one of the plurality of memory cells, wherein during storing of the at least three different data the stepped voltage and the pulse voltage are applied to the control gate and the drain of the selected memory cell, respectively, while a timing of application of the pulse voltage to the drain is controlled relative to a timing of application of the stepped voltage to the control gate, depending on which of the at least three different data is to be stored into the selected memory cell.

Abstract: A method of using a non-volatile semiconductor memory comprising a plurality of row and column lines, a plurality of memory cells disposed at intersections of the row and column lines and a plurality of reference cells disposed on each of the row lines. Each memory cell includes an MOS transistor having a substrate, a spaced-apart drain and source formed on one surface of the substrate, a channel region between the drain and source and a lamination of a tunnel insulating film, a floating gate, an interlayer insulating film and a control gate formed in that order on the channel region.

Abstract: An electrically erasable non-volatile semiconductor memory device comprising a plurality of row lines and column lines, a plurality of memory cells connected in a matrix to the plurality of row lines and column lines, a selection circuit for selecting a desired one of the plurality of memory cells, and write-control circuit for writing data into the plurality of memory cells. The write-control circuit is adapted to preset at least four voltage signals having different voltage values, and to select one of four voltage signals according to a data signal externally applied thereto and applying the selected voltage signal to the selected memory cell. Also included is read-control circuit for reading out data written into the selected memory cell and converting the data read-out from the selected memory cell into a data signal corresponding to one of the four voltage signals.

Abstract: A sliding bearing assembly for a press die set includes a guide post having at least two external grooves disposed parallel to the post axis, each of which has two flat surfaces oriented at 90 degrees to one another. A guide bushing is slidably mounted on the post by guide blocks and a retainer assembly. The guide bushing includes a number of guide blocks equal to the number of grooves in the guide post, and each has a groove opposed to a corresponding groove in the post. The retainer assembly, which is positioned within the guide bushing, includes at least two cross roller bearings, one for each groove on the guide post, mounted on a generally circular frame. The roller bearings are mounted on the frame with the axes of the rollers at such an angle relative to the plane of the frame that the rollers run along the aligned opposed grooves in the guide post and guide blocks.

Abstract: A MOS semiconductor memory device comprises a semiconductor substrate of a first conductive type; impurity diffused regions of a second conductive type different from the first conductive type formed into a plurality of spaced columns extending in a first direction on one surface of the semiconductor substrate and having functions of bit lines; a plurality of columns of element isolation insulating films formed on the impurity diffused regions of the second conductive type, with active regions formed therebetween; a plurality of MOS transistors formed in the active regions aligned in each of a plurality of rows extending in a second direction substantially perpendicular to the first direction, each MOS transistor including a gate formed on a part of the active region with a gate insulating film therebetween and source and drain formed in the impurity diffused regions of the second conductive type; and word lines each connected electrically to the gates of the MOS transistors aligned in each of the rows and ex

Abstract: Disclosed are a projection exposure method which comprises the steps of projecting patterns of first and second photo mask elements by a light including a coherent component, each photo mask element having a pattern of a single-layer structure of one of the phase shift film and the light shielding film on a substrate disposed at a predetermined position such that an optically synthesized pattern of the two patterns is formed on the substrate, and controlling a phase of at least one of a first light portion which projects the pattern of the first photo mask element on the substrate and a second light portion which projects the pattern of the second photo mask element on the substrate, such that said first and second light portions have a predetermined phase difference therebetween and a projection exposure apparatus for carrying out the abovementioned method.

Abstract: A semiconductor memory device to be used as a mask ROM having: a MOS transistor array having MOS transistors disposed in a matrix of rows and columns, the drain-source circuits of the MOS transistors in each row being serially connected; a row selecting decoder for selecting one of the rows; first and second column lines alternately disposed in the row direction, each first column line being connected to one end of the drain-source circuit of each of the MOS transistors disposed in one column, and each second column line being connected to the other end of the drain-source circuit of each of the MOS transistors disposed in the one column; a data reading circuit for reading data stored in the MOS transistor array; a first switching circuit for selectively connecting one of the first column lines to the data reading circuit; a second switching circuit for selectively connecting one of the second column lines to a ground potential; and a column selecting circuit for selecting one of the columns of the MOS transi

Abstract: A mask ROM of the invention comprises: a plurality of memory cells arranged m a matrix; a plurality of word lines, each connecting gates of the memory cells in the lateral direction; a plurality of bit lines which are constructed by serially connecting MOS transistors constructing the memory cells; a row decoder connected to the word lines; and a column decoder connected to the bit lines in which each memory cell is constructed by an MOS transistor and a resistor connected in parallel between the source and drain of each MOS transistor. The content of each memory cell is determined by whether the resistor 8 is cut out or not so that the steps up to the cutting step of the resistors 8 can be standardized while maintaining a high density in integration of the memory cells and the turn-around time can be reduced.

Abstract: An electrical transmission line of the twisted pair of coaxial cable type is provided. One line has a center conductor, a porous plastic dielectric disposed around the outer periphery of the conductor, the dielectric having specific gravity of 0.5 or less, and having a plastic dielectric sheath disposed around the outer periphery of the porous dielectric, the outer sheath having a melting temperature which is 60% or less than the melting temperature of the porous plastic dielectric. The porous plastic dielectric may be in tape form helically wrapped around the conductor, preferably at a wrap angle of 20 degrees or less. The preferred porous dielectric is expanded polytetrafluoroethylene.

Abstract: A photo-mask to be used in a light exposure step for manufacturing semiconductor devices is cleaned by wetting front and rear surfaces of the mask with a liquid, brushing the wetted surfaces with a pair of rotary brushes, wetting the brushed surfaces with an electrolytic solution containing sufficient electrolyte to substantially eliminate electrostatic charge from the surfaces, spraying and immersing the photo-mask in an organic liquid such as an alcohol, and then drying the photo-mask.