Abstract: A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.

Abstract: A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.

Abstract: A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.

Abstract: An arithmetic processing unit includes a register file provided with multiple register windows, an arithmetic executor executes an instruction with data retained in the register file as an operand, and a current window pointer which retains address information specifying a register window which becomes a current window, and a controller. The controller controls the address information retained by the current window pointer is updated, when a window switching instruction for indicating switching of the current window has been decoded. The arithmetic executor reads data in a first register window specified by the address information before being updated and data in a second register window specified by the updated address information from the register file, after the decoding of said window switching instruction has been started until commit of the window switching instruction is started.

Abstract: The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.

Abstract: When all of a plurality of instructions are symmetry instructions, a symmetry instruction issuing unit issues the symmetry instructions to a plurality of reservation stations provided for every different arithmetic operating units until they become full. If it is determined that there is an asymmetry instruction among the plurality of instructions and the residual instructions are the symmetry instructions, an asymmetry instruction issuing unit 56 develops the asymmetry instruction into a multiflow of a previous flow and a following flow, issues the asymmetry instruction to the reservation station provided in correspondence to the specific arithmetic operating unit, and issues the residual symmetry instructions to the plurality of reservation stations provided for every different arithmetic operating units in an issuing cycle different from that of the asymmetry instruction until they become full.

Abstract: A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS of the pair cannot dispatch an instruction to an associated arithmetic pipeline, the other RS dispatches the instruction to that arithmetic pipeline, or delivers its held instruction to the one RS. In case one RS is equipped, plural entries in the RS are divided into groups, and by dynamically changing this grouping according to the dispatch frequency of the instruction to the arithmetic pipelines or the held state of the instructions, the arithmetic pipelines are efficiently utilized. Incidentally, depending on the grouping of the plural entries in the RS, a configuration as if the plural RS were allocated to each arithmetic pipeline may be realized.

Abstract: The present invention relates to a multithread processor. In the multithread processor, when a cache miss occurs on a request related to an instruction in, of a plurality of caches arranged hierarchically, a cache at the lowest place in the hierarchy, with respect to the request suffering the cache miss, a cache control unit notifies an instruction identifier and a thread identifier, which are related to the instruction, to a multithread control unit. When a cache miss occurs on an instruction to be next completed, the multithread control unit makes the switching between threads on the basis of the instruction identifier and thread identifier notified from the cache control unit. This enables effective thread switching, thus enhancing the processing speed.

Abstract: A slider is constituted by a main body made of a metal and a frame member and an end cap made of a synthetic resin. The main body is provided with a rolling groove. The frame member is provided with a return passage and an inner side groove of a direction changing passage. The end cap is provided with an outer side groove of the direction changing passage. A longest outer dimension in a slider width direction between lower end portions of inner legs of the main body is made to be larger than a shortest dimension in the slider width direction between projected portions of the frame member. The frame member is detachably engaged with the main body by putting a side of a leg portion of the main body to and from a side of a frame member horizontal portion by elastically deforming the frame member.

Abstract: When a predetermined instruction is fetched and decoded, an instruction issuing unit develops the instruction operation into a multiflow of a previous flow and a following flow and issues the instruction by in-order. It is held into a reservation station. An instruction executing unit executes the instruction held in the reservation station by out-of-order. Further, an execution result of the instruction is committed by in-order. A multiflow guarantee processing unit guarantees an execution result of the previous flow stored in an allocation register on a register update buffer until the following flow is committed. Even if the previous flow is committed and the allocation register is released, the guaranteeing process is realized by stalling another instruction serving as a next register allocation destination in a decoding cycle until the following flow is committed.

Abstract: Vehicles or ships each carry a magnetic force line sensor, a GPS position detector, and a data transmitter and travel within an observation area transmitting magnetic field data and position data to an earthquake prediction center. A telluric current induction field estimation unit of the earthquake prediction center estimates telluric current induction fields based on the received observation data. A telluric current estimation unit estimates telluric currents based on the results of estimating the telluric current induction fields. A telluric current induction field intensity change pattern generation unit generates patterns indicating the change over time of the intensity of telluric current induction fields. An earthquake prediction unit analyzes the state of distribution of the telluric currents and the patterns of change in the intensities of the telluric current induction fields and estimates a seismofocal zone, seismic intensity, and time of occurrence of a seismic event.

Abstract: A following CC read instruction which is decoded simultaneously with a previous CC update instruction is developed into a multiflow. The first flow is set to a no-operation. A CC renaming update is executed by a CC renaming map update processing unit by the decoding of the previous CC update instruction. The resultant instruction is stored into a CC read instruction multiflow instruction word register. At the next second flow, the CC read instruction is issued from the multiflow instruction word register and, in a state where another instruction is not simultaneously issued, a CC renaming map is referred to by a CC renaming map reference processing unit by the decoding of the CC read instruction.

Abstract: The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.

Abstract: A slider is formed by a metallic main body, a synthetic resin-made frame, and a pair of end caps. The frame is detachably fitted to outer sides of the main body. Ball rolling grooves are provided in the main body. Return paths and inside grooves of a direction changing path are provided in the frame. An outside groove of the direction changing path are provided in each end cap. A paste-like filler is applied to a boundary portion between the main body and the frame and a boundary portion between the frame and the end cap, and is allowed to cure.

Abstract: The present invention relates to a processor system. The processor system is made up of a multithread control unit for selectively making switching among said threads to be executed in an arithmetic unit, a loop predicting unit for predicting a loop of an instruction string on the basis of a processing history of a branch instruction in the thread, and a loop detecting unit for, when the loop predicting unit predicts the loop, detecting the loop on the basis of an instruction. When the loop detecting unit detects the loop, the multithread control unit making the switching from the thread, which is in execution in the arithmetic unit, to a different thread. This prevents a wait condition stemming from the loop from interfering with the execution of other threads without retouching software.

Abstract: An apparatus for efficient parallel executing instruction avoiding the usage of cross bypasses, the apparatus including an instruction buffer for storing instructions, of decoders for decoding, in parallel, the instructions which simultaneously issue from the instruction buffer, executing units for executing the instructions decoded in the decoders, and an instruction-issuing controlling means for controlling the issuing of the instructions in such a way that, when the instructions are executed, one of the plural executing units executes instructions more frequently than the rest of the plural executing units. The apparatus is preferably incorporated in an information processor to superscalar or out-of-order instruction execution.

Abstract: A slider is formed by a metallic main body, a synthetic resin-made frame, and a pair of end caps. The frame is detachably fitted to outer sides of the main body. Ball rolling grooves are provided in the main body. Return paths and inside grooves of a direction changing path are provided in the frame. An outside groove of the direction changing path are provided in each end cap. A paste-like filler is applied to a boundary portion between the main body and the frame and a boundary portion between the frame and the end cap, and is allowed to cure.

Abstract: A slider has a slider main body which has a circulation sleeve whose inner portion forms a rolling element passage by being inserted into a hole penetrating in an axial direction, an end cap which has an outer peripheral track face of a direction changing passage in a curved shape for communicating a load track between two rolling element rolling grooves and the rolling element passage, and is fixed to an axial end portion of the slider main body, and an inner peripheral track member which has an inner peripheral track face of the direction changing passage, and is fitted to the end cap. An end portion of the circulation sleeve is provided with a plurality of positioning projected portions, and the end cap and the inner peripheral track member are provided with recess portions fitted with the positioning projected portions.

Abstract: The present invention relates to a processor system. The processor system is made up of a multithread control unit for selectively making switching among said threads to be executed in an arithmetic unit, a loop predicting unit for predicting a loop of an instruction string on the basis of a processing history of a branch instruction in the thread, and a loop detecting unit for, when the loop predicting unit predicts the loop, detecting the loop on the basis of an instruction. When the loop detecting unit detects the loop, the multithread control unit making the switching from the thread, which is in execution in the arithmetic unit, to a different thread. This prevents a wait condition stemming from the loop from interfering with the execution of other threads without retouching software.

Abstract: The present invention relates to a multithread processor. In the multithread processor, when a cache miss occurs on a request related to an instruction in, of a plurality of caches arranged hierarchically, a cache at the lowest place in the hierarchy, with respect to the request suffering the cache miss, a cache control unit notifies an instruction identifier and a thread identifier, which are related to the instruction, to a multithread control unit. When a cache miss occurs on an instruction to be next completed, the multithread control unit makes the switching between threads on the basis of the instruction identifier and thread identifier notified from the cache control unit. This enables effective thread switching, thus enhancing the processing speed.