Abstract: A semiconductor device includes a base including a substrate and a first insulating layer formed thereon. The base has a first surface and a second surface that is opposite to the first surface, and has an opening that passes through from the first surface to the second surface. A first width of the opening at the first surface is greater than a second width of the opening at the second surface. An electrode formed on the second surface of the base and covers the opening. A metal layer fills the opening and is electrically connected to the electrode.

Abstract: A semiconductor device includes a base including a substrate and a first insulating layer formed thereon. The base has a first surface and a second surface that is opposite to the first surface, and has an opening that passes through from the first surface to the second surface. A first width of the opening at the first surface is greater than a second width of the opening at the second surface. An electrode formed on the second surface of the base and covers the opening. A metal layer fills the opening and is electrically connected to the electrode.

Abstract: An electrode layer is formed on a gate insulating film. An interlayer insulating film is formed on the gate insulating firm. A lower pad is formed by a damascene method. Next, a through hole is formed, and a first interlayer insulating film, which is provided with a projected portion that is in the same pattern as a lower insulating film, is exposed within the through hole at the same time. After etching the first interlayer insulating film so that a part of the projected portion remains as an etching residue, a via insulating film is formed and the via insulating film at the bottom of the through hole is etched. After that, a through electrode is formed by plating an electrode material on the inner side of the via insulating film on the through hole.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, a surface electrode provided on a front surface of the semiconductor substrate through an insulating film, a via, passing through the semiconductor substrate from a rear surface thereof up to the front surface to reach the surface electrode, having a wall including a flange portion inwardly projecting on a front surface portion of the semiconductor substrate, a via insulating film formed on the wall of the via, and a through-electrode embedded inside the via insulating film and electrically connected to the surface electrode, while the via insulating film has portions having different thickness compensating for a step between the flange portion and the remaining portion of the wall, to planarize a contact surface with the through-electrode.

Abstract: A plurality of insulating film rings are selectively formed on a front surface of an Si substrate, and surface pads are formed opposite openings of the insulating film rings. Next, by etching the Si substrate from a back surface, through holes that pass through the openings of the insulating film rings and reach the surface pads are formed. Through electrodes that connect electrically with the surface pads are formed by forming a via insulating film (35) on the sides of the through holes and then filling the through holes with electrode material.

Abstract: The present invention is directed to a semiconductor device including a semiconductor substrate, a through hole penetrating the semiconductor substrate, a base film covering the through hole, a conductive layer disposed on the base film, an insulating film formed on the side wall of the through hole, and a conductive material embedded in the through hole via the insulating film, in which the base film has a stepped portion formed by an opening pattern that selectively exposes the conductive layer therethrough into the through hole, and in which the conductive material is connected electrically to the conductive layer through the opening pattern.

Abstract: An electrode layer is formed on a gate insulating film. An interlayer insulating film is formed on the gate insulating firm. A lower pad is formed by a damascene method. Next, a through hole is formed, and a first interlayer insulating film, which is provided with a projected portion that is in the same pattern as a lower insulating film, is exposed within the through hole at the same time. After etching the first interlayer insulating film so that a part of the projected portion remains as an etching residue, a via insulating film is formed and the via insulating film at the bottom of the through hole is etched. After that, a through electrode is formed by plating an electrode material on the inner side of the via insulating film on the through hole.

Abstract: [Problem] To provide a semiconductor device both capable of greatly reducing the size of a through electrode and capable of reducing the size of a surface electrode and provide a method for manufacturing a semiconductor device capable of reliably bringing a through electrode into contact with a surface electrode regardless of the size of the surface electrode. [Solution] A plurality of insulating film rings (32) are selectively formed on a front surface (13) of an Si substrate (29), and surface pads (33) are formed opposite openings (42) of the insulating film rings (32). Next, by etching the Si substrate (29) from a back surface (14), through holes (56) that pass through the openings (42) of the insulating film rings (32) and reach the surface pads (33) are formed. Through electrodes (17) that connect electrically with the surface pads (33) are formed by forming a via insulating film (35) on the sides of the through holes (56) and then filling the through holes (56) with electrode material.

Abstract: The present invention is directed to a semiconductor device including a semiconductor substrate, a through hole penetrating the semiconductor substrate, a base film covering the through hole, a conductive layer disposed on the base film, an insulating film formed on the side wall of the through hole, and a conductive material embedded in the through hole via the insulating film, in which the base film has a stepped portion formed by an opening pattern that selectively exposes the conductive layer therethrough into the through hole, and in which the conductive material is connected electrically to the conductive layer through the opening pattern.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, a surface electrode provided on a front surface of the semiconductor substrate through an insulating film, a via, passing through the semiconductor substrate from a rear surface thereof up to the front surface to reach the surface electrode, having a wall including a flange portion inwardly projecting on a front surface portion of the semiconductor substrate, a via insulating film formed on the wall of the via, and a through-electrode embedded inside the via insulating film and electrically connected to the surface electrode, while the via insulating film has portions having different thickness compensating for a step between the flange portion and the remaining portion of the wall, to planarize a contact surface with the through-electrode.

Abstract: The present invention provides a method for manufacturing a semiconductor device by which the yield of bumps will be increased. First, an insulation layer, a barrier layer, and a seed layer are sequentially formed on a principal surface of a semiconductor substrate. Then, a protection layer is formed to cover the seed layer and the bumps. Next, portions of the protection layer are removed so that portions of the protection layer covering the sidewalls of the bumps are not removed. Next, the principal surface of the semiconductor substrate is supported by the support through a bonding material, and then a back surface of the semiconductor substrate is polished. Next, the back surface of the semiconductor substrate is polished, and the support and the bonding material are removed.

Abstract: The present invention provides a method for manufacturing a semiconductor device by which the yield of bumps will be increased. First, an insulation layer, a barrier layer, and a seed layer are sequentially formed on a principal surface of a semiconductor substrate. Then, a protection layer is formed to cover the seed layer and the bumps. Next, portions of the protection layer are removed so that portions of the protection layer covering the sidewalls of the bumps are not removed. Next, the principal surface of the semiconductor substrate is supported by the support through a bonding material, and then a back surface of the semiconductor substrate is polished. Next, the back surface of the semiconductor substrate is polished, and the support and the bonding material are removed.

Abstract: In a ferroelectric element, the ferroelectric film is prevented from deteriorating and the interconnect film from lowering in reliability. A ferroelectric element includes a first electrode, a ferroelectric film formed on the first electrode, a second electrode formed on the ferroelectric film, a first hydrogen blocking film formed directly on a surface of the second electrode, a first insulation film formed on the first hydrogen blocking film, a first opening formed in the first hydrogen blocking film exposing a part of the second electrode, a second opening formed in the first insulation film and having a greater diameter than the diameter of the first opening, and an interconnect film connected to the second electrode through the first and second openings.

Abstract: In a ferroelectric element, the ferroelectric film is prevented from deteriorating and the interconnect film from lowering in reliability. A ferroelectric element comprises a first electrode, a ferroelectric film formed on the first electrode, a second electrode formed on the ferroelectric film, a first hydrogen blocking film formed directly on a surface of the second electrode, a first insulation film formed on the first hydrogen blocking film, a first opening formed in the first hydrogen blocking film exposing a part of the second electrode, a second opening formed in the first insulation film and having a greater diameter than the diameter of the first opening, and an interconnect film connected to the second electrode through the first and second openings.

Abstract: In a ferroelectric element, the ferroelectric film is prevented from deteriorating and the interconnect film from lowering in reliability. A ferroelectric element comprises a first electrode, a ferroelectric film formed on the first electrode, a second electrode formed on the ferroelectric film, a first hydrogen blocking film formed directly on a surface of the second electrode, a first insulation film formed on the first hydrogen blocking film, a first opening formed in the first hydrogen blocking film exposing a part of the second electrode, a second opening formed in the first insulation film and having a greater diameter than the diameter of the first opening, and an interconnect film connected to the second electrode through the first and second openings.

Abstract: In a ferroelectric element, the ferroelectric film is prevented from deteriorating and the interconnect film from lowering in reliability. A ferroelectric element comprises a first electrode, a ferroelectric film formed on the first electrode, a second electrode formed on the ferroelectric film, a first hydrogen blocking film formed directly on a surface of the second electrode, a first insulation film formed on the first hydrogen blocking film, a first opening formed in the first hydrogen blocking film exposing a part of the second electrode, a second opening formed in the first insulation film and having a greater diameter than the diameter of the first opening, and an interconnect film connected to the second electrode through the first and second openings.

Abstract: In a method of fabricating a ferroelectric capacitor, a semiconductor substrate is provided. Then, an oxide film is formed on the semiconductor substrate. Next, an adhesion layer, a lower electrode film, a ferroelectric film, an upper electrode film, and an etching mask are formed on the oxide film in that order. A resist pattern is formed on the etching mask. The etching mask is etched using the resist pattern as a mask. Further, the upper electrode film is etched using the etching mask as a mask to form an upper electrode. Next, a protective film is formed on the entire upper surface of a structure obtained above. Then, the protective film is etched back so as to remain a portion thereof on the sidewall of the upper electrode. The ferroelectric film and the lower electrode film is etched to form a lower electrode. Finally, the etching mask and the adhesion layer are removed.

Abstract: This invention provides a dielectric capacitor and its manufacturing method showing a good electric characteristic by preventing an external substance such as a reducing element from entering and diffusing into a dielectric film. In a ferroelectric capacitor C103, a first hydrogen diffusion prevention film 101 can prevent hydrogen generated during the film formation processes of oxide films 7 and 9 from entering and diffusing into a ferroelectric film 4. In addition, since the side wall part of the ferroelectric film 4 is covered with a second hydrogen diffusion prevention film 102, hydrogen is to be completely prevented from entering the internal part of the ferroelectric film 4 from the side wall part thereof. Consequently, the electric characteristic of the ferroelectric film 4 can be kept in good state.

Abstract: A method for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted including a first step for conducting an ashing process at a first temperature e.g. 120° C. or less at which no popping phenomenon happens, for removing the hardened layer, and a second step for conducting an ashing process at a second temperature e.g. 150° C. at which the ashing rate is high, for entirely removing the remaining resist pattern, and apparatus employable for the method for ashing a resist pattern covered by a hardened layer including a mechanism for moving up and down a semiconductor wafer to regulate the temperature of the semiconductor wafer and including a shutter which intervenes between the semiconductor wafer and a heater.

Abstract: A method for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted including a first step for conducting an ashing process at a first temperature e.g. 120° C. or less at which no popping phenomenon happens, for removing the hardened layer, and a second step for conducting an ashing process at a second temperature e.g. 150° C. at which the ashing rate is high, for entirely removing the remaining resist pattern, and apparatus employable for the method for ashing a resist pattern covered by a hardened layer including a mechanism for moving up and down a semiconductor wafer to regulate the temperature of the semiconductor wafer and including a shutter which intervenes between the semiconductor wafer and a heater.