Abstract: A method for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted including a first step for conducting an ashing process at a first temperature e.g. 129° C. or less at which no popping phenomenon happens, for removing the hardened layer, and a second step for conducting an ashing process at a second temperature e.g. 150° C. at which the ashing rate is high, for entirely removing the remaining resist pattern, and apparatus employable for the method for ashing a resist pattern covered by a hardened layer including a mechanism for moving up and down a semiconductor wafer to regulate the temperature of the semiconductor wafer and including a shutter which intervenes between the semiconductor wafer and a heater.

Abstract: A relatively easy manufacturing method of a semiconductor device enabling a contact hole 25 to be formed reliably by self alignment without exposing a gate 11, wherein a plug 20 is adopted to protect an etching stopper film 16 from an etching gas when a preliminary opening 24 is formed by etching an insulating film 22 having an electrical insulating etching stopper film 16 embedded therein.