Patents by Inventor Toshiya Uchida
Toshiya Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11401941Abstract: An air blower capable of preventing a deformation of the vane wheel is provided. A cylindrical holder is provided on rotatable shaft. A vane wheel is provided on the outer circumference of the holder. The holder includes a top section including a plurality of first openings at one end thereof in the axial direction, and includes a flange including a plurality of second openings at the other end thereof, and the vane wheel includes first protrusions to be inserted into the first openings of the holder and fixed to the top section by deformed sections protruding from the first openings, and second protrusions to be inserted into the second openings of the holder and fixed to flange by deformed sections protruding from the second openings.Type: GrantFiled: February 9, 2021Date of Patent: August 2, 2022Assignee: NIDEC COPAL ELECTRONICS CORPORATIONInventors: Yusuke Saito, Masatoshi Obayashi, Kyosuke Saso, Tadashi Okabe, Toshiya Uchida
-
Publication number: 20210164486Abstract: An air blower capable of preventing a deformation of the vane wheel is provided. A cylindrical holder is provided on rotatable shaft. A vane wheel is provided on the outer circumference of the holder. The holder includes a top section including a plurality of first openings at one end thereof in the axial direction, and includes a flange including a plurality of second openings at the other end thereof, and the vane wheel includes first protrusions to be inserted into the first openings of the holder and fixed to the top section by deformed sections protruding from the first openings, and second protrusions to be inserted into the second openings of the holder and fixed to flange by deformed sections protruding from the second openings.Type: ApplicationFiled: February 9, 2021Publication date: June 3, 2021Applicant: NIDEC COPAL ELECTRONICS CORPORATIONInventors: Yusuke Saito, Masatoshi Obayashi, Kyosuke Saso, Tadashi Okabe, Toshiya Uchida
-
Patent number: 9709092Abstract: Provided are a fluid dynamic bearing, a motor, and an optical deflector, for which a fixed shaft can be attached with little axial eccentricity. The bearing (10) is equipped with a fixed shaft (11), a sleeve (20) provided so as to be capable of rotating around the fixed shaft (11), dynamic pressure generating sections (22, 23) provided in the sleeve (20), and a lower case (30) for securing the lower end (11a) of the fixed shaft (11). In addition, the bearing is equipped with a retaining case (40), which has a chuck (52) that retains the upper end (11b) of the fixed shaft (11) secured by the lower case (30), and which can be secured to the lower case (30) in a state that does not generate pressure causing the axial center of the fixed shaft (11) to move.Type: GrantFiled: May 11, 2015Date of Patent: July 18, 2017Assignee: NIDEC COPAL ELECTRONICS CORPORATIONInventors: Takahiro Kikuchi, Takeshi Hijiya, Toshiya Uchida
-
Publication number: 20170074320Abstract: Provided are a fluid dynamic bearing, a motor, and an optical deflector, for which a fixed shaft can be attached with little axial eccentricity. The bearing (10) is equipped with a fixed shaft (11), a sleeve (20) provided so as to be capable of rotating around the fixed shaft (11), dynamic pressure generating sections (22, 23) provided in the sleeve (20), and a lower case (30) for securing the lower end (11a) of the fixed shaft (11). In addition, the bearing is equipped with a retaining case (40), which has a chuck (52) that retains the upper end (11b) of the fixed shaft (11) secured by the lower case (30), and which can be secured to the lower case (30) in a state that does not generate pressure causing the axial center of the fixed shaft (11) to move.Type: ApplicationFiled: May 11, 2015Publication date: March 16, 2017Applicant: NIDEC COPAL ELECTRONICS CORPORATIONInventors: Takahiro KIKUCHI, Takeshi HIJIYA, Toshiya UCHIDA
-
Patent number: 9224487Abstract: A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.Type: GrantFiled: January 24, 2013Date of Patent: December 29, 2015Assignee: Cypress Semiconductor CorporationInventors: Kaoru Mori, Toshiya Uchida
-
Patent number: 8588006Abstract: A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.Type: GrantFiled: August 8, 2012Date of Patent: November 19, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Kobayashi, Toshiya Uchida
-
Patent number: 8449189Abstract: In a gas dynamic pressure bearing mechanism (1) for smoothing rotary motion of a shaft (10) by feeding gas to the bearing clearance between the shaft (10) and a fixed sleeve (20) for supporting the shaft (10) through a herring bone groove (10a), the herring bone groove (10a) is provided in the shaft (10) such that pressure distribution generated in the bearing clearance moves at a high speed. The herring bone groove (10a) consists of N grooves such that N minimal pressure values appearing alternately with maximal pressure values at the positions where the maximal pressure values of dynamic pressure variation appear in the bearing clearance when the shaft (10) rotates have such an interval as it becomes lower than the condensation pressure value.Type: GrantFiled: May 21, 2008Date of Patent: May 28, 2013Assignee: Nidec Copal Electronics CorporationInventors: Akiyoshi Takahashi, Toshiya Uchida
-
Patent number: 8385128Abstract: A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.Type: GrantFiled: February 3, 2011Date of Patent: February 26, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Kaoru Mori, Toshiya Uchida
-
Publication number: 20120300559Abstract: A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.Type: ApplicationFiled: August 8, 2012Publication date: November 29, 2012Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroyuki KOBAYASHI, Toshiya UCHIDA
-
Patent number: 8264881Abstract: A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.Type: GrantFiled: November 24, 2009Date of Patent: September 11, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Kobayashi, Toshiya Uchida
-
Patent number: 8077537Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: GrantFiled: November 4, 2009Date of Patent: December 13, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
-
Publication number: 20110255347Abstract: A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.Type: ApplicationFiled: February 3, 2011Publication date: October 20, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kaoru MORI, Toshiya Uchida
-
Patent number: 8015389Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: GrantFiled: December 19, 2007Date of Patent: September 6, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
-
Patent number: 8004921Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: GrantFiled: November 4, 2009Date of Patent: August 23, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
-
Patent number: 7861043Abstract: The invention relates to a semiconductor memory device and a semiconductor integrated circuit system using the same and a control method of a semiconductor memory device. An object of the invention is to provide a semiconductor memory device which reduces the number of accesses to decrease the burden on a control unit and facilitates circuit board design, a semiconductor integrated circuit system using the same, and a control method of a semiconductor memory device. The semiconductor memory device is configured to have a data input unit to which input data is inputted from outside, a memory unit which stores data, an operation unit which processes a predetermined operation on input data and read data read out from the memory unit, and a data output unit which outputs operation result data obtained at the operation unit to the outside.Type: GrantFiled: February 9, 2006Date of Patent: December 28, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Toshiya Uchida
-
Patent number: 7814294Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: GrantFiled: January 26, 2007Date of Patent: October 12, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
-
Publication number: 20100255614Abstract: In a semiconductor device constituted of stacked semiconductor chips, in order to independently test each of the chips, a second chip is disposed to face a first chip, with a second interconnection terminal thereof connected to a first interconnection terminal of the first chip. First and second external terminals of the first and second chips are formed on surfaces of the first and second chips, the surface being on a same side of the first and second chips. Therefore, even after the first chip and the second chip are pasted together, it is possible to test the first chip and the second chip while operating them independently. Further, since test probes or the like can be brought into contact with the external terminals of the first chip and the second chip from the same side, it is possible to simultaneously test the first chip and the second chip.Type: ApplicationFiled: June 17, 2010Publication date: October 7, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Toshiya UCHIDA
-
Patent number: 7774577Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: GrantFiled: December 19, 2007Date of Patent: August 10, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
-
Publication number: 20100172200Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: November 4, 2009Publication date: July 8, 2010Applicant: FUJITSU LIMITEDInventors: Tomohiro KAWAKUBO, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
-
Publication number: 20100166348Abstract: In a gas dynamic pressure bearing mechanism (1) for smoothing rotary motion of a shaft (10) by feeding gas to the bearing clearance between the shaft (10) and a fixed sleeve (20) for supporting the shaft (10) through a herring bone groove (10a), the herring bone groove (10a) is provided in the shaft (10) such that pressure distribution generated in the bearing clearance moves at a high speed. The herring bone groove (10a) consists of N grooves such that N minimal pressure values appearing alternately with maximal pressure values at the positions where the maximal pressure values of dynamic pressure variation appear in the bearing clearance when the shaft (10) rotates have such an interval as it becomes lower than the condensation pressure value.Type: ApplicationFiled: May 21, 2008Publication date: July 1, 2010Applicant: Nidec Copal Electronics CorporationInventors: Akiyoshi Takahashi, Toshiya Uchida