Abstract: Data is stored into a plurality of first memory blocks, and regeneration data for regenerating this data is stored into a second memory block. In a read operation, either a first operation for reading the data directly from a first memory block selected or a second operation for regenerating the data from the data stored in unselected first memory blocks and the regeneration data stored in the second memory block is performed. This makes it possible to perform an additional read operation on a first memory block during the read operation of this first memory block. Therefore, requests for read operations from exterior can be received at intervals shorter than read cycles. That is, the semiconductor memory can be operated at higher speed, with an improvement in data read rate.

Abstract: A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address input circuit and the drive circuit. A redundant circuit is located near the drive circuit and substitutes other lines including a redundant line for a defective line in the memory array. A defective line information store circuit stores information showing the defective line. A supply circuit supplies information stored in the defective line information store circuit to the redundant circuit via the signal line. This structure enables to transmit an address signal and information regarding a defective line by a common signal line and to reduce the number of wirings and the probability of the penalties of wirings arising.

Abstract: A semiconductor memory device which permits access even during refresh operation and also is low in power consumption. An address input circuit receives an input address, and a readout circuit reads out data from at least part of a subblock group arranged in a column or row direction and specified by the address input via the address input circuit. A refresh circuit refreshes at least part of a subblock group arranged in a row or column direction and intersecting with the subblock group from which data is read out by the readout circuit. A data restoration circuit restores data of a subblock where refresh operation and readout operation take place concurrently, with reference to data from the other subblocks and a parity block.

Abstract: A semiconductor memory device capable of performing transfer operation best suited to applications. An address input circuit receives an input address, and a readout circuit sequentially reads, from m (≦n) banks, data corresponding to one address input via the address input circuit in an automatic manner. A data output circuit outputs the data read by the readout circuit from the m banks to outside as collective data.

Abstract: A mix door D, which is arranged in a limited space defined between an upstream air passage 10 in which an evaporator 3 is installed and a downstream air passage 11 in which a heater core 4 is installed, is of a sliding type. By guiding a door proper 12 by using a cam groove, a seal member 15 bonded to the door proper 12 is pressed against a contacting member 13 only when the door proper 12 assumes its close position. Smoothed operation of the door proper 12 is achieved with a compact construction of a unit, and sealing and temperature controlling performance is increased.

Abstract: A semiconductor memory device and information processing unit that improve speed at which data is written in a semiconductor memory device. A transfer section transfers data in a burst mode. A transferred number setting section sets the number of a plurality of bits of data transferred in the burst mode. A write command input section receives an input write command. A timing section measures time which has elapsed after the write command being input. A write start time setting section sets time which elapses before the writing of data being begun, according to the number of bits of data set by the transferred number setting section.

Abstract: In a command input circuit: m command acquisition units are provided corresponding to first to mth commands, respectively, where m is an integer greater than one; a clock signal supplying unit supplies n clock signals respectively having different phases to the m command acquisition units, where n is an integer greater than one; and a command input unit receives said first to mth commands, and supplies the first to mth commands to the m command acquisition units. Each of the m command acquisition units acquire one of the first to mth commands corresponding to the command acquisition unit in response to one of m edges of the n clock signals corresponding to the one of the first to mth commands. The processing unit performs processing in accordance with the first to mth commands.

Abstract: A semiconductor memory device has a read data line, a write data line, a data holding circuit, and a data writing circuit. The data holding circuit holds data on the write data line, and the data writing circuit writes the data held on the write data line into a memory cell. Further, a semiconductor memory device has a read data line, a write data line, and an address information holding circuit. The address information holding circuit holds address information that is input in relation to write data, and when an access occurs to the address held in the address information holding circuit, data held on the write data line is written into a memory cell corresponding to the address.

Abstract: A resetting circuit includes first and second transistors that respectively receive first and second voltages through gates. The ratio W/L of the second transistor is larger than that of the first transistor. The first and second voltages rise in accordance with the rise of a supply voltage. The second voltage is lower than the first voltage. Since an increase in the current IDS of the first transistor is greater than an increase in the current IDS of the second transistor, an inversion occurs between the current IDSs of the first and second transistors by applying a predetermined supply voltage. Since a reset signal is generated when the values of the currents IDS of the first and second transistors cross, the reset signal can always be generated by the predetermined supply voltage, independent from the threshold voltage of the transistor.

Abstract: The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.

Abstract: A resetting circuit includes first and second transistors that respectively receive first and second voltages through gates. The ratio W/L of the second transistor is larger than that of the first transistor. The first and second voltages rise in accordance with the rise of a supply voltage. The second voltage is lower than the first voltage. Since an increase in the current IDS of the first transistor is greater than an increase in the current IDS of the second transistor, an inversion occurs between the current IDSs of the first and second transistors by applying a predetermined supply voltage. Since a reset signal is generated when the values of the currents IDS of the first and second transistors cross, the reset signal can always be generated by the predetermined supply voltage, independent from the threshold voltage of the transistor.

Abstract: A semiconductor memory device has a read data line, a write data line, a data holding circuit, and a data writing circuit. The data holding circuit holds data on the write data line, and the data writing circuit writes the data held on the write data line into a memory cell. Further, a semiconductor memory device has a read data line, a write data line, and an address information holding circuit. The address information holding circuit holds address information that is input in relation to write data, and when an access occurs to the address held in the address information holding circuit, data held on the write data line is written into a memory cell corresponding to the address.

Abstract: A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.

Abstract: A semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, and a control circuit which controls the internal circuit based on the decoded-command signals. The semiconductor memory device further includes an address-input circuit which latches an address signal in response to the address-latch signal.

Abstract: A mix door D, which is arranged in a limited space defined between an upstream air passage 10 in which an evaporator 3 is installed and a downstream air passage 11 in which a heater core 4 is installed, is of a sliding type. By guiding a door proper 12 by using a cam groove, a seal member 15 bonded to the door proper 12 is pressed against a contacting member 13 only when the door proper 12 assumes its close position. Smoothed operation of the door proper 12 is achieved with a compact construction of a unit, and sealing and temperature controlling performance is increased.

Abstract: One aspect of the present invention is that, when the memory is in the non-power-down state, the supply of clock signals to the data output circuit is limited to the read status after the reception of a read command, and no clock signal supply is performed when either the active status or the write status is in effect. In the best aspect, furthermore, in the read status after the reception of a read command, the supply of clock signals to the data output circuit starts after a number of clock signals corresponding to a set CAS latency following the read command, and stops after a number of clock signals corresponding to a set burst length, after the output of the read out data from the data output circuit starts. Accordingly, even in the non-power-down state, clock signals are only supplied during the time required for the read out data to be actually output from the data output circuit to the outside, whereby it is possible to reduce the number of clock signal supply actions that require large current drive.

Abstract: A power supply adjusting circuit includes a reference voltage supplying part generating a reference voltage based on an external voltage, a plurality of internal voltage generating parts generating a plurality of respective internal voltages based on the reference voltage, and a plurality of control parts corresponding to the internal voltage generating parts, respectively, so as to be able to separately control the internal voltages.

Abstract: A semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, and a control circuit which controls the internal circuit based on the decoded-command signals. The semiconductor memory device further includes an address-input circuit which latches an address signal in response to the address-latch signal.

Abstract: A mix door (5) is arranged in air passages (10, 11) of an automotive air conditioning device. The mix door (5) is arranged to extend in a direction to shut an air flow blown from the upstream air passage (10) and swelled in a downstream direction with a predetermined radius of curvature. The door (5) is guided by arcuate cam grooves (19) and driven upward and downward to achieve open/close operation with the aid of a sliding mechanism (M). Compact construction, reduction in air flow resistance, smoothed handling, high sealing and high temperature controlling are achieved.

Abstract: A mix door (5) is arranged in air passages (10, 11) of an automotive air conditioning device. The mix door (5) is arranged to extend in a direction to shut an air flow blown from the upstream air passage (10) and swelled in a downstream direction with a predetermined radius of curvature. The door (5) is guided by arcuate cam grooves (19) and driven upward and downward to achieve open/close operation with the aid of a sliding mechanism (M). Compact construction, reduction in air flow resistance, smoothed handling, high sealing and high temperature controlling are achieved.