Patents by Inventor Toshiyuki Ohno

Toshiyuki Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879359
    Abstract: A silicon carbide epitaxial wafer (10) of the present invention is a silicon carbide epitaxial wafer including: a silicon carbide substrate (1) and a silicon carbide layer (2) provided on a first principal plane (1A) of the silicon carbide substrate (1) and having a film thickness of 100 ?m or more, wherein a warpage amount of the silicon carbide epitaxial wafer is ?20 ?m or more and 20 ?m or less.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: December 29, 2020
    Inventors: Keiko Masumoto, Satoshi Segawa, Kazutoshi Kojima, Tomohisa Kato, Toshiyuki Ohno
  • Publication number: 20190273136
    Abstract: A silicon carbide epitaxial wafer (10) of the present invention is a silicon carbide epitaxial wafer including: a silicon carbide substrate (1) and a silicon carbide layer (2) provided on a first principal plane (1A) of the silicon carbide substrate (1) and having a film thickness of 100 ?m or more, wherein a warpage amount of the silicon carbide epitaxial wafer is ?20 ?m or more and 20 ?m or less.
    Type: Application
    Filed: February 20, 2019
    Publication date: September 5, 2019
    Inventors: Keiko MASUMOTO, Satoshi SEGAWA, Kazutoshi KOJIMA, Tomohisa KATO, Toshiyuki OHNO
  • Patent number: 10062759
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 28, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 10032871
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 24, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 9846133
    Abstract: Provided are an inspection device that detects with high precision and classifies surface unevenness, step batching, penetrating blade-shaped dislocations, penetrating spiral dislocations, basal plane dislocations, and stacking defects formed in an SiC substrate and an epitaxial layer; and a system. In the inspection device using charged particle beams, a device is used that has an electrode provided between a sample and an objective lens, the device applies a positive or negative voltage to the electrode and obtains images. A secondary electron emission rate is measured and energy EL and EH for the charged particles are found. A first image is obtained using the EH and positive potential conditions. A second image is obtained using the EL and negative potential conditions. A third image is obtained at the same position as the second image, and by using the EL and positive potential conditions.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: December 19, 2017
    Assignee: HITACHI, LTD.
    Inventors: Yoshinobu Kimura, Natsuki Tsuno, Hiroya Ohta, Renichi Yamada, Toshiyuki Ohno, Yuki Mori
  • Patent number: 9508611
    Abstract: In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 29, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinobu Kimura, Natsuki Tsuno, Hiroya Ohta, Renichi Yamada, Hirotaka Hamamura, Toshiyuki Ohno, Hiroyuki Okino, Yuki Mori
  • Publication number: 20160190020
    Abstract: In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.
    Type: Application
    Filed: August 14, 2013
    Publication date: June 30, 2016
    Inventors: Yoshinobu KIMURA, Natsuki TSUNO, Hiroya OHTA, Renichi YAMADA, Hirotaka HAMAMURA, Toshiyuki OHNO, Hiroyuki OKINO, Yuki MORI
  • Publication number: 20160111499
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Application
    Filed: March 29, 2013
    Publication date: April 21, 2016
    Inventors: Digh HISAMOTO, Keisuke KOBAYASHI, Naoki TEGA, Toshiyuki OHNO, Hirotaka HAMAMURA, Mieko MATSUMURA
  • Publication number: 20150303030
    Abstract: Provided are an inspection device that detects with high precision and classifies surface unevenness, step batching, penetrating blade-shaped dislocations, penetrating spiral dislocations, basal plane dislocations, and stacking defects formed in an SiC substrate and an epitaxial layer; and a system. In the inspection device using charged particle beams, a device is used that has an electrode provided between a sample and an objective lens, said device being capable of applying a positive or negative voltage to the electrode and obtaining images. A secondary electron emission rate is measured and energy EL and EH for the charged particles are found. First, an image (first image) is obtained using the EH and positive potential conditions. Next, an image (second image) is obtained using the EL and negative potential conditions. Next, an image (third image) is obtained at the same position as the second image, and by using the EL and positive potential conditions.
    Type: Application
    Filed: November 19, 2012
    Publication date: October 22, 2015
    Inventors: Yoshinobu Kimura, Natsuki Tsuno, Hiroya Ohta, Renichi Yamada, Toshiyuki Ohno, Yuki Mori
  • Publication number: 20130341711
    Abstract: A technique for improving the characteristics of a semiconductor device (UMOSFET) is provided. In the UMOSFET in order to grow an epitaxial growth film on a trench side wall with an even film thickness, a channel is arranged in an optimum direction as a growth surface. For example, a trench is formed on an SiC substrate having a {0001} surface 4° off in a <11-20> direction as a main surface so that a channel surface becomes a {1-100} surface. With this configuration, an epitaxial growth with the even thickness can be conducted on the side wall from which the {1-100} surface of the trench is exposed. As a result, the unevenness of a channel resistance, and the insulation failure of a gate insulating film do not occur, and the yield is improved.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 26, 2013
    Inventors: Daisuke Matsumoto, Toshiyuki Ohno, Hirotaka Hamamura
  • Patent number: 8223212
    Abstract: The hand movement correction apparatus 10 which is capable of correcting hand movement includes: a position variation signal acquisition sections 13 and 17 that acquire a position variation signal; a gain controller 12 that controls the gain of the position variation signal; an exposure determination section 14 that determines whether exposure operation is in progress; a position variation signal switching section 14 that switches the position variation signal; and a hand movement amount calculation section 15 that calculates a hand movement correction amount based on the position variation signal.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: July 17, 2012
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventor: Toshiyuki Ohno
  • Patent number: 8203150
    Abstract: A buffer layer configured of the same conductive semiconductor layers of two or more layers as a drift layer is installed by epitaxial growth between a first semiconductor layer configuring the drift layer that is a layer in which components of the semiconductor device are made and a base substrate including a silicon carbide single crystal wafer. A step of donor concentration is provided at an interface between the drift layer and the buffer layer, an interface between the semiconductor layers configuring the buffer layer, and an interface between the buffer layer and the base substrate and the donor concentration of the drift layer side is lower than that of the base substrate side, thereby making it possible to convert most basal plane dislocations into threading edge dislocations as compared to the drift layer having one layer or the buffer layer configured of one layer.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: June 19, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Toshiyuki Ohno, Natsuki Yokoyama, Hajime Goto
  • Patent number: 8150670
    Abstract: An object of the present invention is to provide a simulator for verifying plural products with common hardware configuration, in which peripheral hardware that can be reused are constituted by hardware and other peripheral hardware is constituted by software simulator, and simulation method. A simulator comprises: a hardware section that includes a peripheral hardware configuration with a structure required for a CPU and OS to operate alone; a software section that simulates the operation of peripheral hardware other than hardware constituting the hardware section as a peripheral hardware model; and an interface board that connects the hardware section and software section.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: April 3, 2012
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventors: Shogo Ishii, Toshiyuki Ohno
  • Publication number: 20100085436
    Abstract: Provided is a hand movement correction apparatus that performs hand movement correction for an image pickup apparatus. The device acquires a variation signal representing the movement of the image pickup apparatus and acquires a first signal obtained by extracting a signal of a frequency not less than a predetermined frequency from the acquired variation signal. The device further acquires a second signal obtained by extracting a signal of a frequency not more than the predetermined frequency from the acquired variation signal and adding the extracted signal to the first signal. The device then switches signal output from the first signal to second signal at the timing at which the start of the exposure processing in the image pickup apparatus is determined and calculates a hand movement correction amount based on the output signal.
    Type: Application
    Filed: February 18, 2008
    Publication date: April 8, 2010
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA SOLUTIONS CORPORATION
    Inventor: Toshiyuki Ohno
  • Publication number: 20090302328
    Abstract: A buffer layer configured of the same conductive semiconductor layers of two or more layers as a drift layer is installed by epitaxial growth between a first semiconductor layer configuring the drift layer that is a layer in which components of the semiconductor device are made and a base substrate including a silicon carbide single crystal wafer. A step of donor concentration is provided at an interface between the drift layer and the buffer layer, an interface between the semiconductor layers configuring the buffer layer, and an interface between the buffer layer and the base substrate and the donor concentration of the drift layer side is lower than that of the base substrate side, thereby making it possible to convert most basal plane dislocations into threading edge dislocations as compared to the drift layer having one layer or the buffer layer configured of one layer.
    Type: Application
    Filed: May 28, 2009
    Publication date: December 10, 2009
    Inventors: Toshiyuki Ohno, Natsuki Yokoyama, Hajime Goto
  • Publication number: 20090167879
    Abstract: The hand movement correction apparatus 10 which is capable of correcting hand movement includes: a position variation signal acquisition sections 13 and 17 that acquire a position variation signal; a gain controller 12 that controls the gain of the position variation signal; an exposure determination section 14 that determines whether exposure operation is in progress; a position variation signal switching section 14 that switches the position variation signal; and a hand movement amount calculation section 15 that calculates a hand movement correction amount based on the position variation signal.
    Type: Application
    Filed: December 22, 2008
    Publication date: July 2, 2009
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA SOLUTIONS CORPORATION
    Inventor: Toshiyuki Ohno
  • Publication number: 20090085044
    Abstract: A manufacturing method is provided for a silicon carbide semiconductor substrate adapted for reduced basal plane dislocations in a silicon carbide epitaxial layer. Between a silicon carbide epitaxial layer for device fabrication (i.e., a drift layer) and a base substrate formed of a silicon carbide single-crystal wafer, a highly efficient dislocation conversion layer through which any basal plane dislocations in the silicon carbide single-crystal wafer are converted into threading edge dislocations very efficiently when the dislocations propagate into the layer epitaxially grown is provided by epitaxial growth. Assigning to the dislocation conversion layer a donor concentration lower than that of the drift layer, therefore, allows the above conversion of a larger number of basal plane dislocations than the case where the drift layer exists alone (without the dislocation conversion layer).
    Type: Application
    Filed: August 20, 2008
    Publication date: April 2, 2009
    Inventors: Toshiyuki Ohno, Natsuki Yokoyama
  • Publication number: 20080288233
    Abstract: An object of the present invention is to provide a simulator for verifying plural products with common hardware configuration, in which peripheral hardware that can be reused are constituted by hardware and other peripheral hardware is constituted by software simulator, and simulation method. A simulator comprises: a hardware section that includes a peripheral hardware configuration with a structure required for a CPU and OS to operate alone; a software section that simulates the operation of peripheral hardware other than hardware constituting the hardware section as a peripheral hardware model; and an interface board that connects the hardware section and software section.
    Type: Application
    Filed: April 29, 2008
    Publication date: November 20, 2008
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA SOLUTIONS CORPORATION
    Inventors: Shogo Ishii, Toshiyuki Ohno
  • Publication number: 20080288232
    Abstract: An object of the present invention is to provide a bridge program capable of achieving common use of the interface between a plurality of modules having different configurations and a hardware model obtained by modeling hardware with software. A bridge program allows a computer to execute: an acquisition step that acquires an operation instruction issued from the module to hardware model; a conversion step that converts the interface of the module into a common interface corresponding to the hardware model; and a discrimination step that acquires the operation instruction acquired by the acquisition step via the common interface into which the interface of the module is converted by the conversion step, discriminates to which hardware model the operation instruction is issued, and outputs the operation instruction to the discriminated hardware model.
    Type: Application
    Filed: April 29, 2008
    Publication date: November 20, 2008
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA SOLUTIONS CORPORATION
    Inventors: Shogo Ishii, Toshiyuki Ohno, Akira Ishitsuka
  • Publication number: 20080281576
    Abstract: There is provided an interface board which synchronizes processings between a CPU board mounting a CPU and peripheral hardware models of peripheral hardware components modeled on a computer. The interface board connects a CPU board and a peripheral hardware simulator with each other. The CPU board has at least one CPU, and the peripheral hardware simulator simulates operation of at least one peripheral hardware component by a peripheral hardware model. The interface board includes: a wait instruction unit that receives an interruption notification from the CPU, then notifies the peripheral hardware model of the interruption notification, and sets the CPU into a wait state; and a release unit that releases the wait state in which the CPU has been set by the wait instruction unit, upon reception of an instruction to release the wait state from the peripheral hardware model which has been notified of the interruption notification.
    Type: Application
    Filed: April 29, 2008
    Publication date: November 13, 2008
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA SOLUTIONS CORPORATION
    Inventors: Toshiyuki Ohno, Akira Ishitsuka, Shogo Ishii