Abstract: A package substrate has a die mounted on a first side. One or more inner solder pads are on an inner portion of a second side. A perimeter of the inner portion is aligned with a perimeter of the die. The one or more inner solder pads are the only solder pads on the inner portion. The one or more inner solder pads number no more than five. A plurality of outer solder pads are on an outer portion of the second side. An average of areas of the one or more inner solder pads is at least five times an average of areas of the one or more inner solder pads. The plurality of outer solder ball pads are for receiving solder ball balls. The outer portion is spaced from the perimeter of the inner portion. The outer portion and the inner portion are coplanar.

Abstract: A package substrate has a die mounted on a first side. One or more inner solder pads are on an inner portion of a second side. A perimeter of the inner portion is aligned with a perimeter of the die. The one or more inner solder pads are the only solder pads on the inner portion. The one or more inner solder pads number no more than five. A plurality of outer solder pads are on an outer portion of the second side. An average of areas of the one or more inner solder pads is at least five times an average of areas of the one or more inner solder pads. The plurality of outer solder ball pads are for receiving solder ball balls. The outer portion is spaced from the perimeter of the inner portion. The outer portion and the inner portion are coplanar.

Abstract: A package structure includes a package substrate having a top surface and a bottom surface. A semiconductor die having a top surface and a bottom surface. The semiconductor die is mounted to the package substrate. The bottom surface of the semiconductor die is adjacent to the top surface of the package substrate. An air gap is between the bottom surface of the package substrate and the bottom surface of semiconductor die.

Abstract: A package structure includes a package substrate having a top surface and a bottom surface. A semiconductor die having a top surface and a bottom surface. The semiconductor die is mounted to the package substrate. The bottom surface of the semiconductor die is adjacent to the top surface of the package substrate. An air gap is between the bottom surface of the package substrate and the bottom surface of semiconductor die.

Abstract: A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.

Abstract: A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.

Abstract: A wafer having a die area and a scribe street is formed. The die area comprises die circuitry and a plurality of bond pads, and the scribe street comprises a test structure. Circuitry of the test structure is probed, and then a passivation layer overlying the surface of the wafer is formed, the passivation layer overlying the plurality of bond pads and overlying the test structure. Openings in the regions of the passivation layer overlying the plurality of bond pads are then formed to expose the plurality of bond pads while retaining the regions of the passivation layer overlying the test structure until singulation of the wafer. Pad metallizations are formed at the plurality of bond pads via the openings in the regions of the passivation layer and the wafer is singulated. The resulting dies may be packaged and the resulting IC packages may be implemented in electronic devices.

Abstract: A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.

Abstract: A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.

Abstract: A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.

Abstract: A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.

Abstract: A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.

Abstract: A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.

Abstract: A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.

Abstract: A conductive via and a method of forming. The conductive via includes a portion located between a conductive contact structure and an overhang portion of a dielectric layer located above the conductive contact structure. In one embodiment, the overhang portion is formed by forming an undercutting layer over the conductive contact structure and then forming a dielectric layer over the conductive contact structure and the undercutting layer. An opening is formed in the dielectric layer and material of the undercutting layer is removed through the opening to create an overhang portion of the dielectric layer. Conductive material of the conductive via is then formed under the overhang portion and in the opening.

Abstract: A conductive via and a method of forming. The conductive via includes a portion located between a conductive contact structure and an overhang portion of a dielectric layer located above the conductive contact structure. In one embodiment, the overhang portion is formed by forming an undercutting layer over the conductive contact structure and then forming a dielectric layer over the conductive contact structure and the undercutting layer. An opening is formed in the dielectric layer and material of the undercutting layer is removed through the opening to create an overhang portion of the dielectric layer. Conductive material of the conductive via is then formed under the overhang portion and in the opening.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.