Patents by Inventor Trent S. Uehling

Trent S. Uehling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7276435
    Abstract: An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: October 2, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Scott K. Pozder, Kevin J. Hess, Ruiqi Tian, Edward O. Travis, Trent S. Uehling, Brett P. Wilkerson, Katie C. Yu
  • Patent number: 7129566
    Abstract: A method of making a semiconductor device includes forming a wafer having a substrate and an interconnect structure over the substrate. The wafer also includes a plurality of die areas and a street located between a first die area of the plurality and a second die area of the plurality. A separation structure that includes metal is located in the interconnect structure. At least a portion of the separation structure is located in a saw kerf of the street. The separation structure is arranged to provide a predefined separation path for separating the first die area during a singulation process.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 31, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Trent S. Uehling, Kevin J. Hess
  • Patent number: 6951801
    Abstract: A process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: October 4, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Scott K. Pozder, Trent S. Uehling, Lakshmi N. Ramanathan
  • Publication number: 20040147097
    Abstract: A process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.
    Type: Application
    Filed: January 27, 2003
    Publication date: July 29, 2004
    Inventors: Scott K. Pozder, Trent S. Uehling, Lakshmi N. Ramanathan
  • Publication number: 20020079595
    Abstract: A pad area of a substrate (50) includes a conductive trace (52) formed on the substrate (50) having a first surface area, the first surface area being of a first solderability. A conductive pad (56) is formed on the first surface area of the conductive trace (52). The conductive pad (56) has a second surface area, the second surface area being of a second solderability. The second solderability is greater than the first solderability. Because of the different solderabilities, a solder bump (46) on the semiconductor die (40) can be reflowed and connected to the second surface area without using a soldermask (28) to contain the melted solder on the second surface area.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 27, 2002
    Inventors: Burton J. Carpenter, Nhat D. Vo, Christopher T. Clark, Willliam M. Stone, Trent S. Uehling, David B. Clegg