Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top surface and side surfaces. A mask layer is disposed over the top surface. A doping support layer is formed to cover part of the fin structure. A first impurity is introduced into a first region of the fin structure covered by the doping support layer, by implanting the first impurity into the doping support layer so that the implanted first impurity is introduced into the first region of the fin structure through the side surfaces.

Abstract: A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film.

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.

Abstract: An embodiment is a method including forming a fin on a substrate, forming a first doped region in a top portion of the fin, the first doped region having a first dopant concentration, and forming a second doped region in a middle and bottom portion of the fin, the second doped region having a second dopant concentration, the second dopant concentration being less than the first dopant concentration.

Abstract: A method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins. In some examples, a mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure. By way of example, a first ion implantation may be performed, at a first temperature, through the group of fins and the test structure. Additionally, a second ion implantation may be performed, at a second temperature greater than the first temperature, through the group of fins and the test structure. In various examples, an interstitial cluster is formed within the group of fins and within the test structure. In some embodiments, an anneal process is performed, where the anneal process serves to remove the interstitial cluster from the group of fins and form at least one dislocation loop within the test structure.

Abstract: Embodiments of a mechanism for forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer are provided. The mechanism involves using one or more low-temperature thermal anneal processes with oxygen sources and one or more microwave anneals to convert a flowable dielectric material to silicon oxide. The low-temperature thermal anneal processes with oxygen sources and the microwave anneals are performed at temperatures below the ranges that could cause significant dopant diffusion, which help dopant profile control for advanced manufacturing technologies. In some embodiments, an implant to generate passages in the upper portion of the flowable dielectric layer is also used in the mechanism.

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract: The present disclosure provides a method for fabricating semiconductor device. The method includes forming a first dielectric layer over a substrate, forming a gate structure over a first portion of the first dielectric layer, forming a sidewall spacer over a second portion of the first dielectric layer and on the gate structure, converting the second portion of the first dielectric layer and an exposed third portion of the first dielectric layer to a first portion of a second dielectric layer and a second portion of the second dielectric layer, respectively, removing the second portion of the second dielectric layer and a portion of the substrate to form a recess in the substrate adjacent the sidewall spacer, forming a source/drain (S/D) feature in the recess and removing the gate electrode and the first portion of the first dielectric layer to form a gate trench.

Abstract: One embodiment of the instant disclosure provides a method for fabrication of fin devices for an integrated circuit, which comprises: forming a plurality of semiconductor fin structures, the fin structures including sidewalls and tops exposed from conformal masking; performing channel implantation at a tilt angle to form a doped region along the sidewalls and the tops of the fin structures, the fin structures being maintained at an elevated temperature during the channel implantation to prevent amorphization thereof during channel implantation; and forming at least one field effect transistor from the fin structures, the field effect transistor having a threshold voltage that is based on the channel implantation.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate; a channel region of a first type conductivity, defined in the fin active region and having a first carrier concentration; and an anti-punch through (APT) feature of the first type conductivity, wherein the APT feature is formed in the semiconductor substrate, is directly underlying the channel region, and has a second carrier concentration greater than the first carrier concentration.

Abstract: One embodiment of the instant disclosure provides a method for fabrication of fin devices for an integrated circuit, which comprises: forming a plurality of semiconductor fin structures, the fin structures including sidewalls and tops exposed from conformal masking; performing channel implantation at a tilt angle to form a doped region along the sidewalls and the tops of the fin structures, the fin structures being maintained at an elevated temperature during the channel implantation to prevent amorphization thereof during channel implantation; and forming at least one field effect transistor from the fin structures, the field effect transistor having a threshold voltage that is based on the channel implantation.

Abstract: Embodiments of a mechanism for forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer are provided. The mechanism involves using one or more low-temperature thermal anneal processes with oxygen sources and one or more microwave anneals to convert a flowable dielectric material to silicon oxide. The low-temperature thermal anneal processes with oxygen sources and the microwave anneals are performed at temperatures below the ranges that could cause significant dopant diffusion, which help dopant profile control for advanced manufacturing technologies. In some embodiments, an implant to generate passages in the upper portion of the flowable dielectric layer is also used in the mechanism.

Abstract: Methods for fabrication of fin devices for an integrated circuit are provided. Fin structures are formed in a semiconductor material, where the fin structures include sidewalls and tops. Dopant implantation is performed at a tilt angle to form a doped region along the sidewalls and the tops of the fin structures, where the semiconductor material is maintained at an elevated temperature during the dopant implantation. The elevated temperature prevents amorphization of the fin structures during the dopant implantation. A field effect transistor is formed from the fin structures. The field effect transistor has a threshold voltage that is based on the dopant implantation.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a gate stack, and performing a pre-amorphous implantation (PAI) process to form an amorphized region on the substrate. The method also includes performing an annealing process to recrystallize the amorphized region after the stress film is formed. The annealing process includes a preheat at a temperature in a range from about 400° C. to about 550° C. and an annealing temperature equal to or greater than about 900° C., and the annealing process recrystallizes the amorphized region.

Abstract: A method of manufacturing a semiconductor device includes performing a pre-amorphous implantation (PAI) process to form an amorphized region on a substrate. The method also includes forming a stress film over the substrate, and performing an annealing process to recrystallize the amorphized region after the stress film is formed. The method further includes forming a recess region on the substrate. The recess region overlies the recrystallized region. The method additionally includes forming an epitaxial stress-inducing material in the recess region.

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract: A display device includes a plurality of gate lines, data lines, first external gate tracking lines, and second external gate tracking lines. The first external gate tracking lines are substantially disposed in a border region of a substrate, and electrically connected with corresponding gate lines. The second external gate tracking lines are substantially disposed in the border region of the substrate, and electrically connected with corresponding gate lines. One of the first external gate tracking lines and a corresponding second external gate tracking line at least partially overlap with each other.

Abstract: An LCD panel transmits the display data to sub-pixels in a zigzag pattern through a data line. The variation of the feed-through voltages of the sub-pixels may be modified by adjusting the ratios of the channel widths and the channel lengths of the TFTs in the sub-pixels to some predetermined ratios, or by adjusting the compensation capacitance to the coupling capacitance of the TFTs of the sub-pixels.

Abstract: The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving dopants from highly doped source and drain regions by annealing for finFET devices are provided. The mechanisms overcome the limitation by shadowing effects of ion implantation for advanced finFET devices. The highly doped source and drain regions are formed by epitaxial growing one or more doped silicon-containing materials from recesses formed in the fins. The dopants are then driven into the LDD regions by advanced annealing process, which can achieve targeted dopant levels and profiles in the LDD regions.