Abstract: In a sense amplifier, local I/O lines are maintained at a predetermined voltage by transistors. Transistors forming a current mirror supply an operating current according to a passing current which flows through transistors, to sense nodes. Transistors forming a current mirror extract an operating current according to the passing current which flows through transistors, from sense nodes. As a result, a voltage difference is generated in sense nodes in accordance with the operating current difference.

Abstract: In a data read operation, a selected memory cell and a reference memory cell are connected to complementary first and second data lines via complementary first and second bit lines, respectively. A differential amplifier supplies passing currents of the memory cell and the reference cell to complementary first and second data buses, and amplifies a passing current difference between the first and second data buses occurring corresponding to an electric resistance difference between the memory cell and reference cell to produce a voltage difference of a polarity corresponding to the level of the stored data of the selected memory cell between first and second nodes.

Abstract: An operating current is supplied from a power supply node to an internal circuit. In a test mode, current supply from a power supply to the power supply node is stopped by a current switch, and an externally adjustable test current is supplied to the power supply node. The test current is set in accordance with an acceptable value of a leakage current in the internal circuit. Evaluation is made as to whether the leakage current in the internal circuit is not greater than the acceptable value, in accordance with an output of a voltage comparison circuit detecting a voltage drop at the power supply node.

Abstract: A nonvolatile semiconductor memory device includes a silicon substrate, bit lines, word lines, and memory cells. The bit line is positioned above the main surface of the silicon substrate and the word line is provided to intersect the bit line. The memory cell is positioned at a region where the bit line and the word line intersect and has one end electrically connected to the bit line and the other end electrically connected to the word line. The memory cell includes a TMR element and an access diode electrically connected in series. The access diode includes an n-type silicon layer and a p-type silicon layer recrystallized by melting-recrystallization and has a pn junction at the interface between the n-type silicon layer and the p-type silicon layer. As a result, a nonvolatile semiconductor memory device reduced in size and having high performance can be manufactured inexpensively.

Abstract: If forward write is performed to a nonvolatile memory cell, a switch signal output circuit outputs a switch signal to a plurality of switch circuits. As a result, corresponding potentials are supplied to a plurality of bit lines, respectively. A potential supply circuit supplies a write potential and a ground potential to the corresponding bit lines, respectively. Therefore, this nonvolatile semiconductor memory device can suppress an unnecessary current generated during data write.

Abstract: In DRAM, a bit line pair are connected to the respective gates of an N channel MOS transistor pair of a read gate, and a write data line pair are connected to the respective gates of an N channel MOS transistor pair of a write gate. Therefore, since neither of the read data line pair and the write data line pair is directly connected to the bit line pair, no data signal on the bit line pair is destroyed by noise occurring on the read data line pair and the write data line pair.

Abstract: At a time a voltage of 6V is applied to all word lines and memory cells connected to a bit line are all simultaneously subjected to a weak write operation using a channel hot electron. Furthermore at a subsequent time a voltage of approximately 2V is applied to a word line and any single memory cell connected to the word line is subjected to a verify operation. The series of the weak write and verify operations are repeated until this memory cell's threshold voltage attains 2V corresponding to an erased condition.

Abstract: A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.

Abstract: A power control unit activates a control signal ST for a circuit block to be set to a standby state before turning off power of the circuit block or a whole chip, and saves an operation result of data processing of the circuit block into a memory unit. When the power is again supplied to the circuit block in the standby state, the power control unit activates a control signal RES after the power supply is started and restores the data saved in the memory unit to the circuit block. Flip-flops in the circuit block are connected in series when the saving or restoring of data is performed, and perform a data transfer operation with a path different from that in a normal operation. Therefore, a semiconductor device can be provided which can rapidly transit to a standby mode having reduced current consumption while holding internal information.

Abstract: If data is to be written to a specific memory cell in each of two adjacent memory cell array blocks, a switch control circuit and a supply circuit supply a first predetermined potential to a first bit line out of first and second bit lines connected to the specific memory cell and supply a second predetermined potential to the second bit line in one memory cell array block. In addition, the first predetermined potential is supplied to the second bit line and the second predetermined potential is supplied to the first bit line in the other memory cell array block. Due to this, this semiconductor memory device can improve throughput while suppressing a current which unnecessarily occurs during data write.

Abstract: A memory cell array has a plurality of memory cells and dummy memory cells. A column select portion switches access control to a memory cell in accordance with a mode control signal. The column select portion selects one memory cell column to connect a first or second bit line connected with one selected memory cell and first and second reference data lines connected with the dummy memory cells to a data read circuit in a first mode. The column select portion connects the first and second bit lines respectively connected to paired two selected memory cells storing data complimentary to each other to the data read circuit in a second mode.

Abstract: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.

Abstract: A plurality of nonvolatile memory cells having gates connected to a same word line, respectively, are connected in series, and connected to adjacent bit lines, respectively. When data is sequentially written to the plurality of nonvolatile memory cells, a bit line select circuit sequentially supplies a write potential outputted from a predetermined potential generation circuit to a plurality of bit lines. The bit line to which the write potential has been supplied once is kept to have the potential. Due to this, this nonvolatile semiconductor memory device can reduce an area occupied by a memory cell array.

Abstract: A current drive circuit operates receiving higher voltage than in a waiting mode at source terminal of a P-channel first driver transistor, when supplying a current to a node connected to a load circuit. In accordance with the rising source potential of the first driver transistor, the gate potential output to the first driver transistor by a gate potential control circuit rises. When the first and second driver transistors are off, a precharge circuit configured with a P-channel MOS transistor precharges the node to a prescribed potential. As a result, the current drive circuit is provided with increased reliability of the gate insulating films of the driver transistors without decreasing the driving current.

Abstract: A semiconductor memory device, a nonvolatile memory device and a magnetic memory device of high reliability are obtained. A semiconductor device as the magnetic memory device includes TMR cells as memory elements, and a stacked interconnection as an interconnection. The stacked interconnection has a first interconnection made of a barrier metal film and a conductor, and a second interconnection made of another barrier metal film and another conductor and stacked on the first interconnection. The stacked interconnection is arranged opposite to the TMR cells. The stacked interconnection is made thicker in the portions facing the TMR cells than in the portions not facing the TMR cells.

Abstract: Each of program cell and memory cells includes a magnetic storage portion of the same configuration. The program cell further includes a state change portion. That is, the program cell has the same structure as the memory cell, except that the state change portion is additionally provided thereto. As such, the program cell can be provided efficiently, as it can be designed the same as the memory cell in terms of the magnetic storage portion and others. The state change portion makes a transition to a fixed state based on an electrical change. Thus, the state change portion prevents program information from being rewritten by a magnetic noise or the like, and ensures stable storage of the program information.

Abstract: An access transistor ATR in an MTJ memory cell, which is one of transistors connected to a read current path, is constituted with a surface-channel, field-effect transistor. The surface-channel, field-effect transistor has a channel resistance lower than a channel-embedded, field-effect transistor, and can reduce an RC load in the read current path. Accordingly, data can be read with a high speed.

Abstract: Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row select signal. Corresponding to a row of memory cells, there is provided a word line connecting to memory cells on corresponding row and transmitting the row select signal, and a word line shunting line electrically connected at predetermined intervals to each word line. Moreover, corresponding to a row of dummy cells and a column of dummy cells, there is provided substrate shunt lines electrically connected to the substrate region. The voltage distribution in the substrate region is eliminated to achieve stable operating characteristics of the memory cell transistor. In addition, a word line is driven at high speed by a word line shunt structure.

Abstract: In one data read operation, data read for reading stored data before and after a predetermined data write magnetic field is applied to a selected memory cell, respectively, is executed, and the data read is executed in accordance with comparison of voltage levels corresponding to the data read operations before and after application of the predetermined data write magnetic field. In addition, data read operations before and after the application of a data write magnetic field are executed using read modify write. It is thereby possible to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path, to improve efficiency of the data read operation with accuracy and to execute a high rate data read operation.

Abstract: An access transistor in an MTJ memory cell, which is one of transistors connected to a read current path, is fabricated with a semiconductor layer formed on an insulating film on a semiconductor substrate SUB, and includes impurity regions, a gate region and a body region. That is, the access transistor is fabricated with an SOI (Silicon On Insulator) structure in order to reduce an off-leak current.