Patents by Inventor Tsukasa Ooishi

Tsukasa Ooishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-volatile memory device conducting comparison operation
    Publication number: 20040037152
    Abstract: The non-volatile memory device includes a current detection circuit for comparing, in data retrieve operation, storage information written in a non-volatile manner in a memory cell row with retrieval information in order to determine whether or not the storage information matches the retrieval information. The current detection circuit compares a data read current flowing through each bit line corresponding to each memory cell of a memory cell row storing the storage information with a data read current flowing through each bit line corresponding to each retrieval memory cell storing the retrieval information.
    Type: Application
    Filed: January 30, 2003
    Publication date: February 26, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Thin film magnetic memory device conducting read operation and write operation in parallel
    Publication number: 20040037110
    Abstract: Bit lines are provided corresponding to columns of MTJ memory cells. Word lines serving as read selection lines and write digit lines serving as write selection lines are provided corresponding to rows of MTJ memory cells. A word line decoder and a digit line decoder are independently provided for the word lines and the write digit lines. The word line decoder selectively activates a word line according to a read address applied to a read port. The digit line decoder selectively activates a write digit line according to a write address applied to a write port.
    Type: Application
    Filed: January 30, 2003
    Publication date: February 26, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Nonvolatile semiconductor memory device having improved redundancy relieving rate
    Publication number: 20040037112
    Abstract: In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the two spare memory cells and connecting these spare memory cells to a sense amplifier, the stored data of one bit is read. A spare memory cell section which is often arranged in an array peripheral portion becomes more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell increases.
    Type: Application
    Filed: February 4, 2003
    Publication date: February 26, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Non-volatile semiconductor memory device having an increased access speed while maintaining the production yield
    Publication number: 20040037113
    Abstract: Bit lines formed from a first metal wiring layer and bit lines formed from a second metal wiring layer are provided as bit lines that intersect with word lines. The bit lines are formed from metal wiring layers and are divided into two layers so that the pitch of the bit lines can be widened. Thereby, a non-volatile semiconductor memory device having an increased access speed while maintaining production yield can be implemented.
    Type: Application
    Filed: December 31, 2002
    Publication date: February 26, 2004
    Inventor: Tsukasa Ooishi
  • Semiconductor memory device operating with low current consumption
    Publication number: 20040027907
    Abstract: In a resistance value variable memory, substrate voltages and/or substrate biases of a digit line drive circuit, a word line drive circuit and a bit line drive circuit for a memory cell array are changed in accordance with an operation mode. A driving power on signal lines connected to memory cells can be increased, and a leakage current during standby can be reduced without increasing a circuit layout area.
    Type: Application
    Filed: April 9, 2003
    Publication date: February 12, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Tsukasa Ooishi
  • Nonvolatile memory device suitable for cache memory
    Publication number: 20040027908
    Abstract: Peripheral circuitry writes/reads input data and output data of L bits (L: integer of at least 2) that is input/output to/from a data node into/from first and second memory cell blocks that are selectively accessed. The peripheral circuitry uses circuit components operating in response to a clock signal to write/read the data by dividing the data writing operation/data reading operation into a plurality of stages and carrying out them in pipelining manner.
    Type: Application
    Filed: January 30, 2003
    Publication date: February 12, 2004
    Inventors: Tsukasa Ooishi, Hiroaki Tanizaki
  • Nonvolatile semiconductor memory device allowing high speed data transfer
    Publication number: 20040027857
    Abstract: Local buses for performing writing/reading of data are provided in correspondence to memory blocks each having a plurality of nonvolatile memory cells, and also circuits for performing writing/reading of data are provided in correspondence to the memory blocks. In addition, data transfer lines for bidirectionally transferring data are provided commonly to the memory blocks, and transfer switch gates for performing data transfer between the memory blocks are provided commonly to the memory blocks. The memory blocks are divided into banks, writing/reading of data on individual memory blocks are performed in units of banks, and parallel execution of writing and reading or of writing/reading and internal transfer is performed. Thus, it is possible to improve data transfer processing efficiency in a nonvolatile semiconductor device.
    Type: Application
    Filed: March 27, 2003
    Publication date: February 12, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Semiconductor device with reduced current consumption in standby state
    Publication number: 20040027902
    Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.
    Type: Application
    Filed: June 27, 2003
    Publication date: February 12, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tsukasa Ooishi, Takaharu Tsuji, Masatoshi Ishikawa, Hideto Hidaka, Hiroshi Kato
  • Ring oscillator having variable capacitance circuits for frequency adjustment
    Patent number: 6690241
    Abstract: A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied. The internal timer includes an oscillator formed of a plurality of inverters connected in ring shape and a variable capacitance circuit for each inverter. Each variable capacitance circuit includes a plurality of sets of transfer gates, fuses and capacitors connected between the output node of the corresponding inverter and a prescribed potential line.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: February 10, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Tomoya Kawagoe, Hideto Hidaka, Mikio Asakura
  • Non-volatile semiconductor memory device conducting read operation using a reference cell
    Publication number: 20040017718
    Abstract: A spare reference cell is provided for a reference cell which is compared to a selected memory cell in read operation. A data read circuit reads storage data of a selected memory cell based on access to the selected memory cell and access to a selected one of the reference cell and the spare reference cell. Selection of the reference cell and the spare reference cell is not fixed according to the result of operation test conducted before a device is used, but can be switched according to various conditions.
    Type: Application
    Filed: January 27, 2003
    Publication date: January 29, 2004
    Inventor: Tsukasa Ooishi
  • Semiconductor memory device in which data are read and written asynchronously with application of address signal
    Publication number: 20040017699
    Abstract: A semiconductor memory device includes an address register circuit for storing a plurality of address signals when an address latch enable signal is active in synchronization with a basic timing signal. When an internal memory selection operation start instructing signal is activated, a selected address signal from the address register circuit is supplied to a row decoder and a column decoder for memory cell selection. While an internal memory selection operation is performed, an address signal is stored in the address register circuit. Application of an address signal and a memory accessing is carried out asynchronously.
    Type: Application
    Filed: February 22, 2001
    Publication date: January 29, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Thin film magnetic memory device and semiconductor integrated circuit device including the same as one of circuit blocks
    Publication number: 20030235070
    Abstract: Shape dummy cells that are designed to have the same dimensions and structures as MTJ memory cells are additionally provided in the peripheral portion of an MTJ memory cell array in which normal MTJ memory cells for storing data are arranged in a matrix. The MTJ memory cells and the shape dummy cells are sequentially arranged so as to have a uniform pitch throughout the entirety. Accordingly, non-uniformity between MTJ memory cells in the center portion and in border portions of the MTJ memory cell array, respectively, after manufacture due to high and low densities of the surrounding memory cells can be eliminated.
    Type: Application
    Filed: May 20, 2003
    Publication date: December 25, 2003
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Tsukasa Ooishi
  • Thin film magnetic memory device conducting read operation by a self-reference method
    Publication number: 20030235069
    Abstract: In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.
    Type: Application
    Filed: December 20, 2002
    Publication date: December 25, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Hideto Hidaka
  • Synchronous semiconductor allowing replacement with redundant memory cell while maintaining access time
    Patent number: 6668345
    Abstract: The higher order bit of the output from an address latch circuit is applied to a predecoder that operates a predecode signal to select a column select line and to a redundancy decoder to select a redundant column. The lower order bit of the address signal is generated by a burst address counter and applied to the predecoder. A comparison result for the higher order bit is calculated in advance at the redundancy decoder. When the lower order bit is applied to the redundancy decoder and the calculation of the comparison result ends, the redundancy determination is output from a redundancy determination unit.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: December 23, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Texas Instruments Incorporated
    Inventors: Tsukasa Ooishi, Hiroya Nakamura
  • Thin film magnetic memory device having dummy cell
    Publication number: 20030223268
    Abstract: A dummy cell has a plurality of dummy magneto-resistance elements which have the same characteristic as a magneto-resistance element, which characteristic changes corresponding to a voltage applied to the opposite ends. In addition, a voltage applied to opposite ends of each dummy magneto-resistance element is made smaller than a voltage applied to opposite ends of a magneto-resistance element of a memory cell. With this, the dummy cell is designed so as to have an intermediate electric resistance between first and second electric resistances.
    Type: Application
    Filed: November 20, 2002
    Publication date: December 4, 2003
    Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA, MITSUBISHI ELECTRIC ENGINEERING COMPANY LIMITED
    Inventors: Hiroaki Tanizaki, Takaharu Tsuji, Tsukasa Ooishi
  • Thin film magnetic memory device having an access element shared by a plurality of memory cells
    Publication number: 20030218901
    Abstract: A tunneling magneto-resistance element forming an MTJ memory cell is connected between a bit line and a strap. In each memory cell column, the strap is shared by the plurality of tunneling magneto-resistance elements in the same row block. The access transistor is connected between strap and ground voltage, and is turned on/off in response to a corresponding word line. Storage data is read from the selected memory cell based on a comparison between results of data reading effected on a memory cell group coupled to the same strap before and after application of a predetermined magnetic field to the selected memory cell.
    Type: Application
    Filed: November 22, 2002
    Publication date: November 27, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Masatoshi Ishikawa
  • Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data
    Publication number: 20030218897
    Abstract: At the time of an operation of writing data to a specific memory cell in a memory block, a semiconductor memory device applies a write voltage for a predetermined period and, after that, performs a verifying operation by using a sense amplifier circuit and a comparator. When it is found as a result of the verifying operation that writing to the memory cell is insufficient, the writing operation is performed again by an instruction of a memory control circuit. At this time, the memory control circuit adjusts a write voltage.
    Type: Application
    Filed: November 19, 2002
    Publication date: November 27, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hiroshi Kato, Yasuhiko Taito, Tsukasa Ooishi, Jun Ohtani
  • Semiconductor memory device capable of accurately writing data
    Publication number: 20030218910
    Abstract: In storing multiple data into a storage area of a first nonvolatile memory cell and into a storage area of a second nonvolatile memory cell in a memory cell array, a first control circuit turns on a switch circuit to supply a predetermined write potential to a bit line, and a second control circuit turns on two switch circuits to supply a source potential to each of two bit lines according to the combination of multiple data to be stored in each memory cell.
    Type: Application
    Filed: November 27, 2002
    Publication date: November 27, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Tsukasa Ooishi
  • Non-volatile semiconductor memory device capable of high-speed data reading
    Publication number: 20030210570
    Abstract: When a non-volatile memory cell which can store two bits per one memory cell and pass current bidirectionally is used, a bias power source potential is provided also to a bit line BL4 adjacent to two bit lines (BL2 and BL2) passing a sense current BL2 and BL3. Switch units are provided corresponding to each bit line for selectively connect to any one of a ground power source line, read power source line or bias power source line. The current flowing from a sense amplifier circuit to the adjacent bit line BL4 via adjacent memory cell can be reduced, and thus the current in the sense amplifier circuit is stabilized quickly. Accordingly, a non-volatile semiconductor memory device allows high-speed data reading operation.
    Type: Application
    Filed: October 30, 2002
    Publication date: November 13, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Jun Ohtani, Tsukasa Ooishi, Hiroshi Kato
  • Fast accessible semiconductor memory device
    Patent number: 6646946
    Abstract: A memory array is divided into a plurality of memory sub blocks in row and column directions. A column selection line is provided in the column direction in a region between blocks. A block decoding circuit generating a local column selection signal is arranged corresponding to each of the memory sub blocks. A main I/O line pair group is provided for each of the memory sub blocks and each column of the memory sub block is connected to the corresponding main I/O line pair in accordance with the local column selection line. Thus, data with a desired bit width can be produced without any increase in area occupied by the array nor decrease in the speed of column access.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: November 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeki Tomishima, Tsukasa Ooishi, Hiroshi Kato