Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A method and a system for mental index prediction are provided. The method includes the following steps. A plurality of images of a subject person are obtained. A plurality of emotion tags of the subject person in the images are analyzed. A plurality of integrated emotion tags in a plurality of predetermined time periods are calculated according to the emotion tags respectively corresponding to the images. A plurality of preferred features are determined according to the integrated emotion tags. A mental index prediction model is established according to the preferred features to predict a mental index according to the emotional index prediction model.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: A method of manufacturing a semiconductor package includes the following steps. A backside redistribution structure is formed, wherein the backside redistribution structure comprises a first dielectric layer, and a redistribution metal layer over the first dielectric layer and comprising a dummy pattern. A semiconductor device is provided over the backside redistribution structure, wherein an active surface of the semiconductor device faces away from the backside redistribution structure, the semiconductor device is electrically insulated from the dummy pattern and overlapped with the dummy pattern from a top view of the semiconductor package. A front side redistribution structure is formed over the semiconductor device, wherein the front side redistribution structure is electrically connected to the semiconductor device. A patterning process is performed on the first dielectric layer to form a marking pattern opening exposing a part of the dummy pattern.

Abstract: A feature identifying method and an electronic device are provided. The method includes: obtaining a plurality of physiological information obtained by measuring a subject at a plurality of time points in one day; converting the plurality of physiological information into a plurality of correlation features respectively; establishing a plurality of first risk prediction models according to the plurality of correlation features, and identifying at least one first correlation feature from the plurality of correlation features according to the plurality of first risk prediction models; establishing a plurality of second risk prediction models according to the at least one first correlation feature, and identifying, according to the plurality of second risk prediction models, at least one second correlation feature capable of predicting a specific disease from the at least one first correlation feature; and outputting the at least one second correlation feature.

Abstract: Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

Abstract: Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

Abstract: The disclosure provides a disease classification method and a disease classification device. The disease classification method includes: inputting samples into a first stage model and obtaining a first stage determination result; inputting first samples determined positive by the first stage model into a second stage high specificity model to obtain second samples determined to be positive and third samples determined to be negative and rule in the second samples; inputting fourth samples determined negative by the first stage model into a second stage high sensitivity model to obtain fifth samples determined to be positive and sixth samples determined to be negative and rule out the sixth samples; obtaining a second stage determination result of the second and sixth samples; and inputting the third and fifth samples not ruled in or ruled out into a third stage model and obtaining a third stage determination result of the third and fifth samples.

Abstract: An electrical system is provided. The electrical system comprises a first phase lock circuit embedded within a first chip for receiving a first periodic signal having a first frequency. The electrical system comprises a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency, wherein the first buffering circuit is configured to provide a third periodic signal having the first frequency to an output terminal of the first chip.

Abstract: An automatic gain adjustor for a hybrid oscillator can be employed to overcome the frequency limitations of hybrid phase lock loops (PLLs). For example, an automatic gain adjustor for a hybrid oscillator can include a hybrid oscillator that is configured to receive a coarse tuning signal and a gain adjustment signal and generate an output signal with any frequency within the specified frequency range of the hybrid PLL. The automatic gain adjustor for a hybrid PLL may further include a fine tuning array that receives one or more fine tuning selection signals and generates a gain adjustment signal that is received by the hybrid oscillator. The fine tuning array generates a gain adjustment signal to adjust the gain of the hybrid oscillator according to an operating frequency range of the hybrid oscillator.

Abstract: A method for deleting data accumulated during Automated Optical Inspection (AOI) used during an AI process uses and applies three systems. The first system obtains an image of a current object under test and writes the image of the current object under test into a current file folder on a hard disk. The current file folder includes information of point-in-time storage. The second system performs AOI on the images of objects under test. If a space available on the hard disk at any time is less than a preset value, the third system deletes file folders that have earliest storage times from the file folders stored in the hard disk. A device and a non-transitory storage medium are also disclosed.

Abstract: Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

Abstract: An electronic package and a manufacturing method thereof are provided, where a plurality of shielding wires are arranged on a carrier and spanning across an electronic component to cover the electronic component, so that the shielding wires serve as a shielding structure to protect the electronic component from the interference of external electromagnetic waves.

Abstract: Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

Abstract: A method and an electronic device of checking drug interaction are provided. The method includes: generating a first odds ratio (OR) between a first drug combination and a hospitalization event, a second OR between a second drug combination and the hospitalization event, and a third OR between a third drug combination and the hospitalization event according to a plurality of medical records; generating a first fraction corresponding to a first drug according to the second OR; generating a second fraction corresponding to a second drug according to the third OR; and outputting the first drug combination in response to the first OR being greater than a first threshold, a sum of the first fraction and the second fraction being greater than a second threshold, and a quotient of the first fraction and the second fraction being less than a third threshold.

Abstract: An electrical system is provided. The electrical system comprises a first phase lock circuit embedded within a first chip for receiving a first periodic signal having a first frequency. The electrical system comprises a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency, wherein the first buffering circuit is configured to provide a third periodic signal having the first frequency to an output terminal of the first chip.

Abstract: A construction method of ribosomal RNA database is provided, including the following steps: selecting a source of nucleic acid sequence database; performing normalization and homogenization on species classification rules; using AI technology for normalized classification and correction; selecting the kingdom to which the sequence species belongs; filtering out redundant sequences and sequences with inconsistent lengths; setting a threshold for unknown bases other than A, T, C or G, and excluding unknown bases that exceed the threshold; and excluding sequences with insufficient classification information.

Abstract: A teammate recommendation method for a multiplayer online game is proposed. The teammate recommendation method includes the steps of: determining one or more characteristic values for each of a plurality of players based on past game performance information of the players; dividing the players into a plurality of groups based on the characteristic values of the players; determining a Key Performance Indicator (KPI) for each of a plurality of combinations of the groups based on teammate information and team ranking of each game in the past game performance information; selecting one of the combinations, which includes a first group that the first player belongs to, based on the KPIs of the combinations; and recommending one or more second players based on the selected combination.

Abstract: An automatic gain adjustor for a hybrid oscillator can be employed to overcome the frequency limitations of hybrid phase lock loops (PLLs). For example, an automatic gain adjustor for a hybrid oscillator can include a hybrid oscillator that is configured to receive a coarse tuning signal and a gain adjustment signal and generate an output signal with any frequency within the specified frequency range of the hybrid PLL. The automatic gain adjustor for a hybrid PLL may further include a fine tuning array that receives one or more fine tuning selection signals and generates a gain adjustment signal that is received by the hybrid oscillator. The fine tuning array generates a gain adjustment signal to adjust the gain of the hybrid oscillator according to an operating frequency range of the hybrid oscillator.