Abstract: A method for flowable oxide deposition is provided. An oxygen source gas is increased as a function of time or film depth to change the flowable oxide properties such that the deposited film is optimized for gap fill near a substrate surface where high aspect ratio shapes are present. The oxygen gas flow rate increases as the film depth increases, such that the deposited film is optimized for planarization quality at the upper regions of the deposited film.

Abstract: Methods of facilitating isolation region uniformity include: patterning a semiconductor substrate to form at least one isolation opening within the semiconductor substrate, the patterning comprising leaving, at least in part, a protective hard mask above a portion of the semiconductor substrate; providing an insulating material within and over the at least one isolation opening, and planarizing the insulating material to facilitate fabricating an isolation region within the semiconductor substrate; stopping the planarizing on the protective hard mask and exposing at least a portion of the protective hard mask above the portion of the semiconductor substrate; and non-selectively removing a remaining portion of the insulating material over the at least one isolation opening and the exposed protective hard mask above the portion of the semiconductor substrate while leaving the insulating material within the at least one isolation opening and exposing upper surfaces of the semiconductor substrate, to facilitate i

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.

Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.

Abstract: A light-emitting diode includes an optical layer formed in an array of substantially equidistant light extracting spots integrated to its multi-layered structure. The array of light extracting spots includes a distribution of juxtaposed hexagon patterns. The layer thickness of the light extracting spots is less than 800 ?.

Abstract: A light-emitting diode includes an optical layer formed in an array of substantially equidistant light extracting spots integrated to its multi-layer structure. The array of light extracting spots includes a distribution of juxtaposed hexagon patterns. The layer thickness of the light extracting spots is less than 800 ?, and preferably around 500 ?.

Abstract: A method for detecting a periodic signal in a communication system. The method includes converting a time domain digitized signal to obtain a corresponding frequency domain digitized signal, quantizing at least two symbols of the frequency domain digitized signal to obtain quantization information, utilizing the quantization information to compute a detection metric for periodic signal detection, and determining that a periodic signal is detected if the detection metric is greater than a predetermined threshold.

Abstract: A method includes converting a received time domain digital signal to a corresponding frequency domain digital signal, calculating phase angles of tones of at least one symbol of the frequency domain digital signal when a symbol timing offset exists, and calculating at least one differential phase offset (DPO). A DPO is the difference between two consecutive gaps, a gap being the difference between the phase angle of a tone of the symbol of the frequency domain digital signal when the timing offset of the symbol exists and a correct phase angle of the tone of the symbol of the frequency domain digital signal. The method estimates the symbol timing offset with at least one DPO.

Abstract: In a method of forming an as-grown active p-type III-V nitride compound layer, a substrate is introduced and heated in a reaction chamber. N2 carrier gas and reactive compounds including a source compound of a group III element, a nitrogen source compound, and a p-type impurity are fed in the reaction chamber. A chemical reaction occurs to form an as-grown active p-type III-V nitride compound layer.

Abstract: A method includes converting a received time domain digital signal to a corresponding frequency domain digital signal, calculating phase angles of tones of at least one symbol of the frequency domain digital signal when a symbol timing offset exists, and calculating at least one differential phase offset (DPO). A DPO is the difference between two consecutive gaps, a gap being the difference between the phase angle of a tone of the symbol of the frequency domain digital signal when the timing offset of the symbol exists and a correct phase angle of the tone of the symbol of the frequency domain digital signal. The method estimates the symbol timing offset with at least one DPO.

Abstract: A method for detecting a periodic signal in a communication system. The method includes converting a time domain digitized signal to obtain a corresponding frequency domain digitized signal, quantizing at least two symbols of the frequency domain digitized signal to obtain quantization information, utilizing the quantization information to compute a detection metric for periodic signal detection, and determining that a periodic signal is detected if the detection metric is greater than a predetermined threshold.

Abstract: The present invention is directed to methods and systems for providing an accurate estimate of the channel capacity that may be performed for each symbol rate tested during line probe. In addition, an optimal symbol rate under a set of conditions may be determined using the capacities for each tested symbol rate. In the G.SHDSL (or other) standard, provisions may be made for rate negotiation to take place between two communicating modems after a line probe session. The present invention provides an approach to rate negotiation that implements an approximation of channel capacity using a geometric mean calculation. The capacity for a plurality of M frequency sub-bands may be computed to find an estimate of channel capacity for a rate of interest. The sub-bands may be any segment of a total N frequency bands found with a discrete Fourier transform (DFT) or other method of spectrum estimation.

Abstract: The present invention is directed to methods and systems for determining maximum power backoff for modems operating according to G.SHDSL and other standards using frequency domain geometric signal to noise ratio (SNR). In one example, a G.SHDSL standard may specify a minimum power back off (PBO) that may be required for modem implementation. Although the standard specifies the minimum back off, it is desirable to be able to increase the PBO beyond this level. The reasons for this may include reduced power consumption and reduced crosstalk generated by a modem. The present invention discloses a method and system for determining an absolute maximum power PBO that may be tolerated and still meet bit error rate (BER) and/or other requirements. The present invention implements a geometric mean to compute SNR in a frequency domain over a pass-band of a transmit spectrum.