Patents by Inventor Tsung-Min Huang
Tsung-Min Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9601346Abstract: A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.Type: GrantFiled: July 10, 2015Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Min Huang, Chung-Ju Lee, Yung-Hsu Wu
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Patent number: 9576851Abstract: A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the low-k dielectric layer, where the opening exposes a portion of the substrate. The method may also include filling the opening with a copper alloy and forming a copper-containing layer over the copper alloy and the low-k dielectric layer. An etch rate of the copper-containing layer may be greater than an etch rate of the copper alloy. The method may additionally include patterning the copper-containing layer to form interconnect features over the low-k dielectric layer and the copper alloy.Type: GrantFiled: August 5, 2015Date of Patent: February 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Min Huang, Chung-Ju Lee, Tsung-Jung Tsai
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Patent number: 9576893Abstract: A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.Type: GrantFiled: December 3, 2014Date of Patent: February 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Min Huang, Chung-Ju Lee
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Patent number: 9558927Abstract: A method for reducing contaminants in a semiconductor device is provided. The method includes cleaning the semiconductor substrate. The cleaning includes rotating the semiconductor substrate and dispersing an aerosol at a predetermined temperature to a surface of the semiconductor substrate or a layer formed on the substrate to be cleaned. The aerosol includes a chemical having a predetermined pressure and a gas having a predetermined flow rate.Type: GrantFiled: July 15, 2013Date of Patent: January 31, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hua Huang, Tsung-Min Huang, Chung-Ju Lee
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Patent number: 9514979Abstract: A method includes forming a mandrel layer over a target layer, and etching the mandrel layer to form mandrels. The mandrels have top widths greater than respective bottom widths, and the mandrels define a first opening in the mandrel layer. The first opening has an I-shape and includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. Portions of the first opening that are unfilled by the spacers are extended into the target layer.Type: GrantFiled: August 31, 2015Date of Patent: December 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Min Huang, Chung-Ju Lee, Yung-Hsu Wu
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Publication number: 20160343668Abstract: A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein. A metal layer is formed on the first dielectric material layer, wherein the metal layer fills the plurality of vias. The metal layer is etched such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal features aligned with the plurality of vias respectively. A self-assembled monolayer film is formed on surfaces of the plurality of metal features.Type: ApplicationFiled: August 1, 2016Publication date: November 24, 2016Inventors: Tsung-Min Huang, Chung-Ju Lee
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Patent number: 9502249Abstract: A method, e.g., of forming and using a mask, includes forming an inverse mask over a dielectric layer; forming a mask layer conformally over the inverse mask; removing horizontal portions of the mask layer; and after removing the horizontal portions, simultaneously etching the inverse mask and vertical portions of the mask layer. The etching the inverse mask is at a greater rate than the etching the vertical portions of the mask layer. The etching the inverse mask removes the inverse mask, and the etching the vertical portions of the mask layer forms a mask comprising rounded surfaces distal from the dielectric layer. Recesses are formed in the dielectric layer using the mask. Locations of the inverse mask correspond to fewer than all locations of the recesses.Type: GrantFiled: February 18, 2016Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Min Huang, Chung-Ju Lee
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Publication number: 20160276153Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers. The method further includes patterning the first photoresist to form a second mask pattern, and patterning the first hard mask layer using the first mask pattern and the second mask pattern in a same patterning step.Type: ApplicationFiled: May 31, 2016Publication date: September 22, 2016Inventors: Tsung-Min Huang, Chung-Ju Lee
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Patent number: 9449839Abstract: The present disclosure relates to a method of forming a pattern on a semiconductor substrate. One or more layers are formed over the semiconductor substrate. A first self-assembled monolayer (SAM) layer is formed over the one or more layers, wherein the first SAM layer exhibits a first SAM pattern. At least a first of the one or more layers is patterned using the first SAM layer as a first etch mask to form first pillars in the first of the one or more layers and then removing the first SAM layer. A second self-assembled monolayer (SAM) layer is formed along sidewall portions of the first pillars after the first SAM layer has been removed, wherein the second SAM layer exhibits a second SAM pattern that differs from the first SAM pattern and where the second SAM layer differs in material composition from the first SAM layer.Type: GrantFiled: November 10, 2014Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Min Huang, Chung-Ju Lee, Chien-Hua Huang
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Patent number: 9418862Abstract: A method includes forming a resist over a substrate, resulting in a layer of resist scum between the resist and the substrate. The method further includes forming trenches in the resist, wherein at least a portion of the layer of resist scum remains between the trenches and the substrate. The method further includes forming a first material layer in the trenches, wherein the first material layer has a higher etch resistance than the resist in an etching process. The method further includes performing the etching process to the first material layer, the resist, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.Type: GrantFiled: November 6, 2015Date of Patent: August 16, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Min Huang, Chieh-Han Wu, Chung-Ju Lee, Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu
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Publication number: 20160225664Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.Type: ApplicationFiled: January 25, 2016Publication date: August 4, 2016Inventors: Chien-Hua Huang, Chung-Ju Lee, Tsung-Min Huang
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Patent number: 9406614Abstract: A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein. A metal layer is formed on the first dielectric material layer, wherein the metal layer fills the plurality of vias. The metal layer is etched such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal features aligned with the plurality of vias respectively. A self-assembled monolayer film is formed on surfaces of the plurality of metal features.Type: GrantFiled: March 8, 2013Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Min Huang, Chung-Ju Lee
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Publication number: 20160172196Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A a dielectric layer is formed over a substrate. An interlayer is formed over the dielectric layer. A first photoresist layer with a first opening is formed over the interlayer and a second photoresist layer having a second opening is formed over the first photoresist layer. Spacers are formed along sidewalls of the first opening and the second opening. A first trench is formed in the interlayer by using the spacer along the first opening as an etch mask. A second trench is formed in the interlayer by using the spacer along the second opening as an etch mask. The first trench and the second trench are extended down into the dielectric layer as a lower portion and an upper portion, respectively, of a dielectric trench.Type: ApplicationFiled: February 8, 2016Publication date: June 16, 2016Inventors: Chung-Ju LEE, Chih-Tsung SHIH, Jeng-Horng CHEN, Shinn-Sheng YU, Tsung-Min HUANG, Anthony YEN
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Patent number: 9368348Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers. The method further includes patterning the first photoresist to form a second mask pattern, and patterning the first hard mask layer using the first mask pattern and the second mask pattern in a same patterning step.Type: GrantFiled: October 1, 2013Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Min Huang, Chung-Ju Lee
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Publication number: 20160163548Abstract: A method, e.g., of forming and using a mask, includes forming an inverse mask over a dielectric layer; forming a mask layer conformally over the inverse mask; removing horizontal portions of the mask layer; and after removing the horizontal portions, simultaneously etching the inverse mask and vertical portions of the mask layer. The etching the inverse mask is at a greater rate than the etching the vertical portions of the mask layer. The etching the inverse mask removes the inverse mask, and the etching the vertical portions of the mask layer forms a mask comprising rounded surfaces distal from the dielectric layer. Recesses are formed in the dielectric layer using the mask. Locations of the inverse mask correspond to fewer than all locations of the recesses.Type: ApplicationFiled: February 18, 2016Publication date: June 9, 2016Inventors: Tsung-Min Huang, Chung-Ju Lee
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Publication number: 20160148874Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.Type: ApplicationFiled: February 1, 2016Publication date: May 26, 2016Inventors: Chao-Hsien Peng, Tsung-Min Huang, Hsiang-Huan Lee, Shau-Lin Shue
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Publication number: 20160064240Abstract: A method includes forming a resist over a substrate, resulting in a layer of resist scum between the resist and the substrate. The method further includes forming trenches in the resist, wherein at least a portion of the layer of resist scum remains between the trenches and the substrate. The method further includes forming a first material layer in the trenches, wherein the first material layer has a higher etch resistance than the resist in an etching process. The method further includes performing the etching process to the first material layer, the resist, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.Type: ApplicationFiled: November 6, 2015Publication date: March 3, 2016Inventors: Tsung-Min Huang, Chien-Han Wu, Chung-Ju Lee, Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu
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Patent number: 9275873Abstract: A method, e.g., of forming and using a mask, includes forming an inverse mask over a dielectric layer; forming a mask layer conformally over the inverse mask; removing horizontal portions of the mask layer; and after removing the horizontal portions, simultaneously etching the inverse mask and vertical portions of the mask layer. The etching the inverse mask is at a greater rate than the etching the vertical portions of the mask layer. The etching the inverse mask removes the inverse mask, and the etching the vertical portions of the mask layer forms a mask comprising rounded surfaces distal from the dielectric layer. Recesses are formed in the dielectric layer using the mask. Locations of the inverse mask correspond to fewer than all locations of the recesses.Type: GrantFiled: September 26, 2013Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Min Huang, Chung-Ju Lee
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Patent number: 9257282Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is formed over a substrate. An interlayer is formed over the dielectric layer. A first photoresist layer with a first opening is formed over the interlayer and a second photoresist layer having a second opening is formed over the first photoresist layer. Spacers are formed along sidewalls of the first opening and the second opening. A first trench is formed in the interlayer by using the spacer along the first opening as an etch mask. A second trench is formed in the interlayer by using the spacer along the second opening as an etch mask. The first trench and the second trench are extended down into the dielectric layer as a lower portion and an upper portion, respectively, of a dielectric trench.Type: GrantFiled: May 2, 2014Date of Patent: February 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tsung Shih, Tsung-Min Huang, Chung-Ju Lee, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
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Patent number: 9252049Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.Type: GrantFiled: March 6, 2013Date of Patent: February 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Hsien Peng, Tsung-Min Huang, Hsiang-Huan Lee, Shau-Lin Shue