Abstract: A method includes forming a mandrel layer over a target layer, and etching the mandrel layer to form mandrels. The mandrels have top widths greater than respective bottom widths, and the mandrels define a first opening in the mandrel layer. The first opening has an I-shape and includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. Portions of the first opening that are unfilled by the spacers are extended into the target layer.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.

Abstract: A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.

Abstract: A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.

Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers. The method further includes patterning the first photoresist to form a second mask pattern, and patterning the first hard mask layer using the first mask pattern and the second mask pattern in a same patterning step.

Abstract: Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method.

Abstract: A method, e.g., of forming and using a mask, includes forming an inverse mask over a dielectric layer; forming a mask layer conformally over the inverse mask; removing horizontal portions of the mask layer; and after removing the horizontal portions, simultaneously etching the inverse mask and vertical portions of the mask layer. The etching the inverse mask is at a greater rate than the etching the vertical portions of the mask layer. The etching the inverse mask removes the inverse mask, and the etching the vertical portions of the mask layer forms a mask comprising rounded surfaces distal from the dielectric layer. Recesses are formed in the dielectric layer using the mask. Locations of the inverse mask correspond to fewer than all locations of the recesses.

Abstract: The present disclosure relates to a method of forming a pattern on a semiconductor substrate. One or more layers are formed over the semiconductor substrate. A first self-assembled monolayer (SAM) layer is formed over the one or more layers, wherein the first SAM layer exhibits a first SAM pattern. At least a first of the one or more layers is patterned using the first SAM layer as a first etch mask to form first pillars in the first of the one or more layers and then removing the first SAM layer. A second self-assembled monolayer (SAM) layer is formed along sidewall portions of the first pillars after the first SAM layer has been removed, wherein the second SAM layer exhibits a second SAM pattern that differs from the first SAM pattern and where the second SAM layer differs in material composition from the first SAM layer.

Abstract: A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.

Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

Abstract: A method for reducing contaminants in a semiconductor device is provided. The method includes cleaning the semiconductor substrate. The cleaning includes rotating the semiconductor substrate and dispersing an aerosol at a predetermined temperature to a surface of the semiconductor substrate or a layer formed on the substrate to be cleaned. The aerosol includes a chemical having a predetermined pressure and a gas having a predetermined flow rate.

Abstract: A method and apparatus for controlling a silicon nitride etching bath provides the etching bath including phosphoric acid heated to an elevated temperature. The concentration of silicon in the phosphoric acid is controlled to maintain a desired level associated with a desired silicon nitride/silicon oxide etch selectivity. Silicon concentration is measured while the silicon remains in soluble form and prior to silica precipitation. Responsive to the measuring, fresh heated phosphoric acid is added to the etching bath when necessary to maintain the desired concentration and silicon nitride:silicon oxide etch selectivity and prevent silica precipitation. The addition of fresh heated phosphoric acid enables the etching bath to remain at a steady state temperature. Atomic absorption spectroscopy may be used to monitor the silicon concentration which may be obtained by diluting a sample of phosphoric acid with cold deionized water and measuring before silica precipitation occurs.

Abstract: A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.

Abstract: A method of forming an interconnect structure of an integrated circuit including providing a first dielectric layer disposed on a semiconductor substrate. A via (or via hole) is etched in the first dielectric layer. A conductive layer including copper is formed that fills the via hole and has a first portion that is disposed on a top surface of the first dielectric layer. A trench is formed in the first portion of the conductive layer to pattern a copper interconnect line disposed on the first dielectric layer. The trench is filled with a second dielectric material. In an embodiment, a barrier layer is self-formed during the removal of a masking element used in the etching of the trench.

Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.

Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.

Abstract: A method and system for controlling a silicon nitride etching bath provides the etching bath including phosphoric acid heated to an elevated temperature. The concentration of silicon in the phosphoric acid is controlled to maintain a desired level associated with a desired silicon nitride/silicon oxide etch selectivity. Silicon concentration is measured while the silicon remains in soluble form and prior to silica precipitation. Responsive to the measuring, fresh heated phosphoric acid is added to the etching bath when necessary to maintain the desired concentration and silicon nitride:silicon oxide etch selectivity and prevent silica precipitation. The addition of fresh heated phosphoric acid enables the etching bath to remain at a steady state temperature. Atomic absorption spectroscopy may be used to monitor the silicon concentration which may be obtained by diluting a sample of phosphoric acid with cold deionized water and measuring before silica precipitation occurs.

Abstract: A lead-free valve of faucet and process of manufacturing same is provided. The faucet includes a valve comprising a stainless steel sleeve including a rim; a stainless steel cartridge including a stepped-diameter opening with the rim seated thereon, two opposite peripheral ports, and a soldered joint for joining the sleeve, the rim, and the cartridge together; a stainless steel stem secured to a handle and co-rotated therewith, the stem including a bottom tab; a plastic disc first retaining member including a slit; a ceramic oval second retaining member including two opposite cavities and a slot aligned with the slit, and the tab inserted through the slit into the slot to join the stem, the first retaining member, and the second retaining member together; a ceramic disc abutting member including two opposite, spaced through holes; and a plastic seat for urging the abutting member against the second retaining member.