Abstract: A current command value in a period from a time when a relay switch is turned on until charging of an inverter capacitor is completed is set to a value smaller than a value corresponding to the smallest one of rated currents of components included in a circuit, and is set to a value smaller than a maximum current value in a safe operating area of a switching element.

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage is provided. For this, a first deposition film (2) of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate (1) of a first conductivity type. Formed on the first deposition film (2) is a second deposition film (31) that comprises a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film (32) formed on the second deposition film, which comprises a second region that is wider than the selectively removed first region, a high concentration source region (5) of a first conductivity type and a low concentration gate region (11) of a second conductivity type. A low concentration base region (4) of a first conductivity type is formed in contact with the first deposition film (2) in the first and second regions.

Abstract: A current command value in a period from a time when a relay switch is turned on until charging of an inverter capacitor is completed is set to a value smaller than a value corresponding to the smallest one of rated currents of components included in a circuit, and is set to a value smaller than a maximum current value in a safe operating area of a switching element.

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.

Abstract: A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage is provided. For this, a first deposition film (2) of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate (1) of a first conductivity type. Formed on the first deposition film (2) is a second deposition film (31) that comprises a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film (32) formed on the second deposition film, which comprises a second region that is wider than the selectively removed first region, a high concentration source region (5) of a first conductivity type and a low concentration gate region (11) of a second conductivity type. A low concentration base region (4) of a first conductivity type is formed in contact with the first deposition film (2) in the first and second regions.

Abstract: A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.

Abstract: This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.

Abstract: A low on-resistance silicon carbide semiconductor device is provided to include an ohmic electrode of low contact resistance and high adhesion strength formed on a lower surface of silicon carbide. Specifically, the silicon carbide semiconductor device includes at least an insulating film, formed on an upper surface of a silicon carbide substrate, and includes at least an ohmic electrode, formed of an alloy comprising nickel and titanium, or formed of a silicide comprising nickel and titanium, and which is formed on the lower surface of the silicon carbide substrate.

Abstract: A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

Abstract: The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

Abstract: In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.

Abstract: In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.

Abstract: A low on-resistance silicon carbide semiconductor device is provided that includes an ohmic electrode of low contact resistance and high adhesion strength formed on a lower surface of silicon carbide. The silicon carbide semiconductor device includes: at least an insulating film 7, formed on an upper surface of silicon carbide; and at least an ohmic electrode 12, formed of an alloy comprising nickel and titanium, or a silicide comprising nickel and titanium, and which is formed on the lower surface of the silicon carbide.

Abstract: This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.

Abstract: In the SiC vertical MOSFET having a low-concentration p-type deposition film provided therein with a channel region and a base region resulting from reverse-implantation to n-type through ion implantation, dielectric breakdown of gate oxide film used to occur at the time of off, thereby preventing a further blocking voltage enhancement. This problem has been resolved by interposing of a low-concentration n-type deposition film between a low-concentration p-type deposition film and a high-concentration gate layer and selectively forming of a base region resulting from reverse-implantation to n-type through ion implantation in the low-concentration p-type deposition film so that the thickness of deposition film between the high-concentration gate layer and each of channel region and gate oxide layer is increased.

Abstract: The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

Abstract: A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

Abstract: A semiconductor device (1) includes an n-type silicon carbide substrate (2) of a high impurity concentration, an n-type silicon carbide layer (3) of a low impurity concentration disposed on the substrate, a first n-type silicon carbide region (4) of a first impurity concentration disposed on the surface of the n-type silicon carbide layer, first p-type silicon carbide regions (5) disposed as adjoined to the opposite sides of the first n-type silicon carbide region, a second n-type silicon carbide region (6) disposed selectively from the surface through the interior of the first p-type silicon carbide region, polycrystalline silicon (7) short-circuiting the first p-type silicon carbide region (5) to the second n-type silicon carbide region (6), a gate electrode (8) and a third n-type silicon carbide region (10), wherein the components thereof are individually constructed in a vertical DMOS structure.

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.