Abstract: A print management apparatus includes a print management unit, a storage unit, and a print controller. The print management unit acquires print information of printing processing performed by an image forming apparatus and performs management of the processing. The storage unit temporarily stores print information acquired by the print management unit. The print controller performs control such that print information that is temporarily stored is transmitted sequentially to the image forming apparatus. Even in a case where the print controller has generated, by mistake, a notification indicating completion of transmission, even though the print controller has not completed transmission of print information, the print management unit detects that there is a page that has not been printed by the image forming apparatus, on the basis of information on the progress of printing from the image forming apparatus.

Abstract: A comparison function-equipped memory element includes: a memory circuit that stores comparison object data; a comparison circuit that compares the comparison object data held in the memory circuit with comparison data and outputs the comparison result; and a write circuit that writes the comparison object data into the memory circuit under control of a write control signal during write operation, and overwrites the comparison data into the memory circuit when a mask control signal indicates mask operation during comparison operation.

Abstract: A power supply device is capable of transferring AC power in a noncontact manner to a secondary coil of a power receiving device. The power supply device includes an AC power supply that outputs the AC power. The AC power supply includes a DC/AC conversion unit that converts DC power to the AC power, which has a predetermined frequency. A primary coil receives the AC power. A control unit controls the AC power output from the AC power supply. The control unit is configured to suspend the output of the AC power from the AC power supply or decrease the AC power based on input power, input current value, output power, or output current value of the DC/AC conversion unit and a power factor or a current difference of the input current value and the output current value.

Abstract: A power receiving device receives alternating current power in a wireless manner from a power supply device including an alternating current power supply and a primary coil. The power receiving device includes a secondary coil, a variable load, an impedance conversion unit, and an acknowledgement unit. Under a situation in which the acknowledgement unit acknowledges that the value of the alternating current power output from the alternating current power supply is unvaried, the impedance of the impedance conversion unit is variably controlled when an electrical property that is dependent on a relative position of the primary coil and the secondary coil varies.

Abstract: A power receiving device receives alternating current power in a wireless manner from a power supply device including a primary coil that receives the alternating current power. The power receiving device includes a secondary coil, a variable load, a first impedance conversion unit, a second impedance conversion unit, a fixed load, and a switch. The switch switches an output destination, to which the alternating current power received by the secondary coil is output from the first impedance conversion unit, to the fixed load or to the second impedance conversion unit and the variable load.

Abstract: A power-receiving device includes a secondary coil, which wirelessly receives AC power from a power-supply device having a primary coil, a variable load, in which an impedance changes in accordance with the power value of the input power, a PFC circuit having a first switching element, and a DC/DC converter having a second switching element. The PFC circuit rectifies the AC power received by the secondary coil and improves the power factor by adjusting the duty cycle in switching operation of the first switching element in accordance with the impedance fluctuation of the variable load. The DC/DC converter is configured to convert the voltage of the DC power to a different voltage and output the converted voltage to the variable load, and to adjust the duty cycle in switching operation of the second switching element in accordance with the impedance fluctuation of the variable load.

Abstract: A power-receiving device includes a secondary-side coil which can receive a first alternating current power without contact from a power-sending device having a primary side coil into which first alternating current power is input. The power-receiving device comprises a first power transmission path, a second power transmission path, a common path positioned in common with the first and second power transmission paths, and a voltage regulator arranged on the common path. The voltage regulator rectifies the first alternating current power received by the secondary coil or the second alternating current power from a connecting portion, converts the rectified power to a predetermined specific voltage value, and outputs the power.

Abstract: A non-contact power transmission device equipped with a ground-side device and a vehicle-side device. The ground-side device has a primary-side coil to which alternating-current power is input. The vehicle-side device includes a secondary-side coil, a battery, a secondary-side matching device, and a charging device. The secondary-side coil receives alternating-current power from the primary-side coil in a non-contact manner. The secondary-side matching device is provided between the secondary-side coil and the battery, and has a predetermined fixed inductance and fixed capacitance. The charging device has a switching element that performs a switching operation with a prescribed cycle. The charging device adjusts the duty ratio of the switching operation in accordance with the impedance of a load.

Abstract: There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second level in accordance with a first clock signal when the plurality of input signals is in a second state. The second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level.

Abstract: A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied.

Abstract: A contactless power transmission device includes a switching unit that switches a power transmission line so that a first power is transmitted through the first line when an AC power supply outputs a first AC power and so that a second power is transmitted through a second line when the AC power supply outputs a second AC power. An impedance conversion unit is arranged on the second line that converts an impedance from an output of the AC power supply to a variable load when the second power is transmitted through the second line to approach an impedance from the output of the AC power supply to the variable load when the first power is transmitted through the first line.

Abstract: The data transmission circuit includes: a plurality of local bit line pairs through which data is read simultaneously; a plurality of voltage change detection circuits provided for the plurality of local bit line pairs; a global bit line pair; a plurality of column selection circuits configured to select one of the local bit line pairs and connect the selected local bit line pair to the global bit line pair; and a sense amplifier connected to the global bit line pair. The sense amplifier is controlled by a sense amplifier activation signal to which the outputs of the plurality of voltage change detection circuits are connected, whereby the voltage of a selected read data line pair is amplified using discharge of a non-selected read data line pair, to achieve high-speed read.

Abstract: The abnormality detection system is provided for detecting an abnormality of an object. The abnormality detection system includes a high-frequency power source, a primary coil, a secondary coil and a controller. The high-frequency power source supplies power. The primary coil receives the power supplied from the high-frequency power source. The secondary coil is mounted to the object in noncontact with the primary coil for receiving power supplied from the primary coil. The controller is operable to detect the power received by the secondary coil and also to determine whether or not an abnormality is present in the object based on the detected power.

Abstract: In a semiconductor memory device, an update data control circuit is provided, which selectively couples a physical address input data line or an effective address input data line to a common input data line coupled to a physical address cell that stores a physical address page number. A control terminal of an update circuit of the physical address cell is coupled to a page size cell that stores page size information via an update control circuit, to control a write port of the physical address cell with the page size cell.

Abstract: A print management apparatus includes a print management unit, a storage unit, and a print controller. The print management unit acquires print information of printing processing performed by an image forming apparatus and performs management of the processing. The storage unit temporarily stores print information acquired by the print management unit. The print controller performs control such that print information that is temporarily stored is transmitted sequentially to the image forming apparatus. Even in a case where the print controller has generated, by mistake, a notification indicating completion of transmission, even though the print controller has not completed transmission of print information, the print management unit detects that there is a page that has not been printed by the image forming apparatus, on the basis of information on the progress of printing from the image forming apparatus.

Abstract: A first write transistor has a source connected to a power-supply node, a drain connected to a first local bit line, and a gate connected to a second write global bit line. A second write transistor has a source connected to the power-supply node, a drain connected to a second local bit line, and a gate connected to a first write global bit line. A third write transistor has a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate receiving a first control signal. A fourth write transistor has a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate receiving the first control signal. A read circuit is connected to the first and second local bit lines and first and second read global bit lines.

Abstract: In a state where a signal (IN) is at “H” and an NMOS transistor (403) is on, when a signal (PCLK) changes to “H” and a PMOS transistor (401) turns off, an output node (N1) becomes coupled to a word-line activation signal (WACTCLK) via the NMOS transistor (403). When the word-line activation signal (WACTCLK) changes to “L,” a word line signal (MWL) changes to “L.” Since the signal (PCLK) is at “H” and the NMOS transistor (405) is on, this NMOS transistor (405) can assist discharging of the word-line activation signal (WACTCLK) to a ground voltage.

Abstract: A power supply control circuit which can cut off a power supply independently is provided for each column in a memory cell array. The power supply control circuit is controlled by a circuit which is provided for each column and determines whether or not it is necessary to hold information, whereby a power supply for a memory cell which does not need to hold information is cut off.

Abstract: There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second level in accordance with a first clock signal when the plurality of input signals is in a second state. The second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level.

Abstract: A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied.