Patents by Inventor Tsuyoshi Matsuda

Tsuyoshi Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080258058
    Abstract: A double-biprism electron interferometer is an optical system which dramatically increases the degree of freedom of a conventional one-stage electron interferometer. The double-biprism electron interferometer, however, is the same as the optical system of the single electron biprism interferometer in terms of the one-dimensional shape of an electron hologram formed by filament electrodes, the direction of an interference area and the azimuth of the interference fringes. In other words, the longitudinal direction of the interference area is determined corresponding to the direction of the filament electrodes, and the azimuth of the interference fringes only coincides with and is in parallel with the longitudinal direction of the interference area.
    Type: Application
    Filed: January 27, 2006
    Publication date: October 23, 2008
    Inventors: Ken Harada, Tetsuya Akashi, Yoshihiko Togawa, Tsuyoshi Matsuda, Noboru Moriya
  • Publication number: 20080068387
    Abstract: An image processing device for realizing more realistic pictures of explosions in video game devices and the like. Objects displaying such pictures of explosions are formed of spherical polygons (R1, R2, R3, . . . ) and planar polygons (S1, S2, S3, . . . ). Pictures of explosions are realized by alternately arranging these spherical polygons and planar polygons with the lapse in time. Preferably, pictures of polygons are realized by arranging the spherical polygons in layers on the boundary of the planar polygons.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 20, 2008
    Inventors: Makoto Yamamoto, Kenji Tohma, Shinobu Hayashi, Tsuyoshi Matsuda, Yoshitaka Maeyama, Tomoya Takasugi
  • Publication number: 20070272861
    Abstract: The present invention provides a technique enabling to control fringe spacing s and an interference width W independently of each other, which are important parameters for an interferometer using an electron biprism. In the present invention, two electron biprisms 9u, 9b are used in two stages along the optical axis, and fringe spacing s and an interference width W are controlled independently of each other by controlling a voltage applied to an electrode of each of the electron biprisms. Also Fresnel diffraction can be suppressed.
    Type: Application
    Filed: January 7, 2005
    Publication date: November 29, 2007
    Applicant: RIKEN
    Inventors: Ken Harada, Tatsuya Akashi, Yoshihiko Togawa, Tsuyoshi Matsuda
  • Publication number: 20070176140
    Abstract: A first polishing composition is used in chemical mechanical polishing for removing one part of the portion of a conductive layer positioned outside a trench. A second polishing composition is used in chemical mechanical polishing for removing the remaining part of the portion of a conductive layer positioned outside the trench and the portion of a barrier layer positioned outside the trench. The first polishing composition contains a specific surfactant, a silicon oxide, a carboxylic acid, an anticorrosive, an oxidizing agent, and water. The second polishing composition contains colloidal silica, an acid, an anticorrosive, and a completely saponified polyvinyl alcohol.
    Type: Application
    Filed: September 30, 2004
    Publication date: August 2, 2007
    Inventors: Tsuyoshi Matsuda, Tatsuhiko Hirano, Junhui Oh, Atsunori Kawamura, Kenji Sakai
  • Publication number: 20060134908
    Abstract: A method for polishing an object to form wiring for a semiconductor device includes: removing part of an outside portion of a conductor layer through chemical and mechanical polishing to expose an upper surface of a barrier layer; and removing a remaining part of the outside portion of the conductor layer and an outside portion of the barrier layer through chemical and mechanical polishing to expose an upper surface of an insulator layer. When removing part of the outside portion of the conductor layer, the upper surface of the object is chemically and mechanically polished using a first polishing composition containing a film forming agent. Subsequently, the upper surface of the object is washed to remove a protective film formed on an upper surface of the conductor layer by the film forming agent in the first polishing composition. Thereafter, the upper surface of the object is chemically and mechanically polished again using a second polishing composition containing the film forming agent.
    Type: Application
    Filed: November 4, 2005
    Publication date: June 22, 2006
    Inventors: Junhui Oh, Atsunori Kawamura, Tsuyoshi Matsuda, Tatsuhiko Hirano, Katsunobu Hori, Kenji Sakai
  • Publication number: 20060022974
    Abstract: An image processing device for realizing more realistic pictures of explosions in video game devices and the like. Objects displaying such pictures of explosions are formed of spherical polygons (R1, R2, R3, . . . ) and planar polygons (S1, S2, S3, . . . ). Pictures of explosions are realized by alternately arranging these spherical polygons and planar polygons with the lapse in time. Preferably, pictures of polygons are realized by arranging the spherical polygons in layers on the boundary of the planar polygons.
    Type: Application
    Filed: September 30, 2005
    Publication date: February 2, 2006
    Inventors: Makoto Yamamoto, Kenji Tohma, Shinobu Hayashi, Tsuyoshi Matsuda, Yoshitaka Maeyama, Tomoya Takasugi
  • Patent number: 6980207
    Abstract: An image processing device for realizing more realistic pictures of explosions in video game devices and the like. Objects displaying such pictures of explosions are formed of spherical polygons (R1, R2, R3, . . . ) and planar polygons (S1, S2, S3, . . . ). Pictures of explosions are realized by alternately arranging these spherical polygons and planar polygons with the lapse in time. Preferably, pictures of polygons are realized by arranging the spherical polygons in layers on the boundary of the planar polygons.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: December 27, 2005
    Assignee: Kabushiki Kaisha Sega Enterprises
    Inventors: Makoto Yamamoto, Kenji Tohma, Shinobu Hayashi, Tsuyoshi Matsuda, Yoshitaka Maeyama, Tomoya Takasugi
  • Publication number: 20050215060
    Abstract: A polishing composition contains a deterioration inhibitor for inhibiting deterioration of polishing capability of the polishing composition, an abrasive, and water. The deterioration inhibitor is at least one selected from polysaccharide and polyvinyl alcohol. The polysaccharide is starch, amylopectin, glycogen, cellulose, pectin, hemicellulose, pullulan, or elsinan. Among them, pullulan is preferable. The abrasive is at least one selected from aluminum oxide and silicon dioxide, preferably at least one selected from fumed silica, fumed alumina, and colloidal silica. The polishing composition can be suitably used in polishing for forming wiring a semiconductor device.
    Type: Application
    Filed: March 21, 2005
    Publication date: September 29, 2005
    Applicant: Fujimi Incorporated
    Inventors: Junhui Oh, Atsunori Kawamura, Tsuyoshi Matsuda, Tatsuhiko Hirano, Kenji Sakai, Katsunobu Hori
  • Publication number: 20050208761
    Abstract: A polishing composition contains a surface irregularity-inhibitor, silicon dioxide, an acid, an oxidant, and water. The surface irregularity-inhibitor is at least one selected from, for example, stored polysaccharides and extracellular polysaccharides. The silicon dioxide is, for example, colloidal silica, fumed silica, or precipitated silica. The acid is at least one selected from, for example, nitric acid, hydrochloric acid, sulfuric acid, lactic acid, acetic acid, oxalic acid, citric acid, malic acid, succinic acid, butyric acid, and malonic acid. The oxidant is, for example, hydrogen peroxide, persulfate, periodate, perchlorate, nitrate salt, or an oxidative metallic salt. The polishing composition can be suitably used in polishing for forming wiring in a semiconductor device.
    Type: Application
    Filed: March 21, 2005
    Publication date: September 22, 2005
    Applicant: Fujimi Incorporated
    Inventors: Junhui Oh, Atsunori Kawamura, Tsuyoshi Matsuda, Tatsuhiko Hirano, Kenji Sakai, Katsunobu Hori
  • Publication number: 20050108949
    Abstract: A polishing composition of the present invention, to be used in polishing for forming wiring in a semiconductor device, includes: a specific surfactant; a silicon oxide; at least one selected from the group consisting of carboxylic acid and alpha-amino acid; a corrosion inhibitor; an oxidant; and water This polishing composition is capable of suppressing the occurrence of the dishing.
    Type: Application
    Filed: September 29, 2004
    Publication date: May 26, 2005
    Inventors: Tsuyoshi Matsuda, Tatsuhiko Hirano, Junhui Oh, Atsunori Kawamura, Kenji Sakai
  • Patent number: 6773476
    Abstract: A polishing composition comprising: (a) at least one abrasive selected from the group consisting of silicon dioxide and aluminum oxide, (b) at least one organic compound selected from the group consisting of a polyethylene oxide, a polypropylene oxide, a polyoxyethylene alkyl ether, a polyoxypropylene alkyl ether, a polyoxyethylenepolyoxypropylene alkyl ether and a polyoxyalkylene addition polymer having a C≡C triple bond, represented by the formula (1): wherein each of R1 to R6 is H or a C1-10 alkyl group, each of X and Y is an ethyleneoxy group or a propyleneoxy group, and each of m and n is a positive number of from 1 to 20, (c) at least one polishing accelerating compound selected from the group consisting of citric acid, oxalic acid, tartaric acid, glycine, &agr;-alanine and histidine, (d) at least one anticorrosive selected from the group consisting of benzotriazole, benzimidazole, triazole, imidazole and tolyltriazole, (e) hydrogen peroxide, and (f) water.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: August 10, 2004
    Assignee: Fujimi Incorporated
    Inventors: Kenji Sakai, Kazusei Tamai, Tadahiro Kitamura, Tsuyoshi Matsuda, Katsuyoshi Ina
  • Publication number: 20040104912
    Abstract: An image processing device for realizing more realistic pictures of explosions in video game devices and the like. Objects displaying such pictures of explosions are formed of spherical polygons (R1, R2, R3, . . . ) and planar polygons (S1, S2, S3, . . . ). Pictures of explosions are realized by alternately arranging these spherical polygons and planar polygons with the lapse in time. Preferably, pictures of polygons are realized by arranging the spherical polygons in layers on the boundary of the planar polygons.
    Type: Application
    Filed: October 9, 2003
    Publication date: June 3, 2004
    Applicant: Kabushiki Kaisha Sega Enterprises
    Inventors: Makoto Yamamoto, Kenji Tohma, Shinobu Hayashi, Tsuyoshi Matsuda, Yoshitaka Maeyama, Tomoya Takasugi
  • Publication number: 20040084414
    Abstract: A polishing method for reliably polishing a polishing target and a polishing composition used for polishing are provided. The polishing method of the present invention includes a first step in which the polishing target is polished with a first polishing composition, a second step in which the polishing target is polished with a second polishing composition, and a third step in which polishing target is polished with a third polishing composition. The polishing target is a multilayer, which includes an insulation layer, which has trenches on its surface, a barrier layer located on the insulation layer, and a conductor layer located on the barrier layer. In the first step, part of a portion of the conductor layer located outside the trenches is removed. In the second step, a remaining part of the portion of the conductor layer located outside the trenches is removed. In the third step, a portion of the barrier layer located outside the trenches is removed.
    Type: Application
    Filed: August 18, 2003
    Publication date: May 6, 2004
    Inventors: Kenji Sakai, Kazusei Tamai, Atsunori Kawamura, Tsuyoshi Matsuda, Tatsuhiko Hirano, Katsuyoshi Ina
  • Patent number: 6664965
    Abstract: An image processing device for realizing more realistic pictures of explosions in video game devices and the like. Objects displaying such pictures of explosions are formed of spherical polygons (R1, R2, R3, . . . ) and planar polygons (S1, S2, S3, . . . ). Pictures of explosions are realized by alternately arranging these spherical polygons and planar polygons with the lapse in time. Preferably, pictures of polygons are realized by arranging the spherical polygons in layers on the boundary of the planar polygons.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: December 16, 2003
    Assignee: Kabushiki Kaisha Sega Enterprises
    Inventors: Makoto Yamamoto, Kenji Tohma, Shinobu Hayashi, Tsuyoshi Matsuda, Yoshitaka Maeyama, Tomoya Takasugi
  • Publication number: 20030051413
    Abstract: A polishing composition comprising:
    Type: Application
    Filed: July 23, 2002
    Publication date: March 20, 2003
    Applicant: FUJIMI INCORPORATED
    Inventors: Kenji Sakai, Kazusei Tamai, Tadahiro Kitamura, Tsuyoshi Matsuda, Katsuyoshi Ina
  • Patent number: 5283215
    Abstract: The present invention relates to a refractory for casting process composed mainly of 0.3 to 10 wt % light burned magnesia, 3 to 30 wt % micro fine calcined alumina, and the remainder of either sintered alumina, fused alumina and MgO-Al.sub.2 O.sub.3 spinel or sintered alumina and MgO-Al.sub.2 O.sub.3 spinel or fused alumina and MgO-Al.sub.2 O.sub.3 spinel.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: February 1, 1994
    Assignees: Ceramic Co., Ltd. Harima, Nippon Steel Corporation
    Inventors: Kiyoshiro Hosokawa, Hitoshi Nishiwaki, Kouichi Nishi, Seiji Hanagiri, Shiro Sukenari, Takenori Nakamichi, Naoki Tsutsui, Tsuyoshi Matsuda, Kouzou Akao
  • Patent number: 4642461
    Abstract: A field emission type electron microscope using a multi-stage acceleration tube wherein an acceleration voltage to be applied to at least one, always inclusive of a first-stage acceleration electrode, of acceleration electrodes is changed in interlocked relationship with a change in a field emission voltage to be applied to a field emission electrode, so that power of an electrostatic lens can be kept constant.
    Type: Grant
    Filed: November 29, 1984
    Date of Patent: February 10, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Junji Endo, Akira Tonomura, Susumu Ozasa, Tsuyoshi Matsuda, Chikara Kimura, Nobuyuki Osakabe