Abstract: In a semiconductor flip-chip package having a semiconductor die 104 as part of a substrate assembly, a lid 110 (or lid assembly) and substrate 102 are supported with respect to each other so as to prevent tilting and teetering of the lid during socketing, testing, application of heat sinks, and so forth. Yet the lid and substrate do not adhere, so as to reduce cracking of solder joints due to thermal cycling induced by repeated system power on-off. In some embodiments, an adhesion prohibitor 315, 325 may be explicitly applied so that a support 314, 324 does not adhere to both lid and substrate; in other embodiments, the support 314, 324 may be prevented from adhering to both lid and substrate by a separate curing step. That is, fabrication methods (FIGS. 4A, 4B) involving an adhesive prohibitor may involve a single curing step for the support material and a lid-attach adhesive 112 (such as a polymer), while fabrication methods (FIGS.

Abstract: A system (100) for manufacturing product, in which a first work station (101) is operable to perform a first manufacturing action on the product parts; this first station has a first entrance (101a) and a first exit 101b). A second work station (102) is operable to perform a second manufacturing action on the product parts; this second station has a second entrance (102a) and a second exit (102b). A transport line (103) between the first exit and the second entrance is operable to move the product parts under computer control. A chamber (104) encloses a portion of the line and is constructed so that the transport achieves a balanced throughput from the first station to the second station, while the product parts are exposed to computer-controlled environmental conditions (110) during transport through the chamber. The balanced throughput in the chamber is achieved by waiting lines for the product with computer-controlled monitors (105a) for product parts' positions and times in the chamber.

Abstract: A metal interconnect structure (100) comprising a bond pad (110) of copper; a body (103) of eutectic alloy in contact with the bond pad, this alloy including copper; and a contact pad (120) comprising copper in contact with the alloy body. When the eutectic alloy is tin/lead, the alloy includes copper in an amount greater than 0.08 weight percent and less than 2.0 weight percent. When the eutectic alloy is tin/silver, the alloy includes copper in an amount greater than 0.9 weight percent and less than 2.0 weight percent.

Abstract: Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

Abstract: A device comprising a workpiece (401) with a surface (401a) including a center (402) and an array of bond pads (420), further an array of interconnects (405) of uniform height. Each of these interconnects comprises an elongated wire loop, which has both wire ends (440, 450) attached to one of the bond pads, respectively, and its major diameter (460) approximately normal to the workpiece surface. A substantial number of the loops has an orientation approximately normal to the vector (410) from the workpiece center to the respective bond pad; this number includes more than 30% of the loops located along the workpiece perimeter and more than 10% of the total loops. Examples of workpieces are a semiconductor device, an integrated circuit (IC) chip, and a semiconductor device package.

Abstract: A system (100) for manufacturing product, in which a first work station (101) is operable to perform a first manufacturing action on the product parts; this first station has a first entrance (101a) and a first exit 101b). A second work station (102) is operable to perform a second manufacturing action on the product parts; this second station has a second entrance (102a) and a second exit (102b). A transport line (103) between the first exit and the second entrance is operable to move the product parts under computer control. A chamber (104) encloses a portion of the line and is constructed so that the transport achieves a balanced throughput from the first station to the second station, while the product parts are exposed to computer-controlled environmental conditions (110) during transport through the chamber. The balanced throughput in the chamber is achieved by waiting lines for the product with computer-controlled monitors (105a) for product parts' positions and times in the chamber.

Abstract: Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

Abstract: A raised solder-mask-defined (SMD) pad configured for receiving a solder ball on a laminate electronic circuit board and a method of creating the raised SMD pad on a laminate electronic circuit board. The method may comprise forming a base bump, covering the base bump with a conductive bump layer and layering a surrounding material over an extended edge of the conductive bump layer. The surrounding material is patterned to expose a pad face and of a portion of the sides of the conductive bump layer, such that the pad face is disposed above the surface of the surrounding material. The surrounding material may be patterned by a photolithography operation or alternatively, a laser-drill operation.

Abstract: A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back surface of the die with a low-modulus thermal gel, and the second material is disposed towards the perimeter of the lid. The second material has a modulus of elasticity greater than the modulus of elasticity of the first material, and preferable, at least twice that of the first material.

Abstract: A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back surface of the die with a low-modulus thermal gel, and the second material is disposed towards the perimeter of the lid. The second material has a modulus of elasticity greater than the modulus of elasticity of the first material, and preferably, at least twice that of the first material.

Abstract: A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back surface of the die with a low-modulus thermal gel and the second material is disposed towards the perimeter of the lid. The second material has a modulus of elasticity greater than the modulus of elasticity of the first material, and preferably, at least twice that of the first material.

Abstract: A plastic package for use in semiconductor devices, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each of said terminals. The bumps are made of reflowable metal and have approximately uniform height. An adherent layer of polymer material covers the package surface and surrounds each of the bumps to form a solid meniscus. The layer has a thickness between a quarter and one half of the bump height. An analogous methodology applies to plastic assembly boards.

Abstract: Electronic devices of improved reliability having a substrate of electrically insulating material, further an integrated circuit chip with a periphery and a surface. Using a layer of polymeric material, the chip surface is mounted on the substrate surface. The polymeric material protrudes beyond the chip periphery and spreads some distance along the substrate surface. A metal layer is on the substrate surface, this layer is shaped as a band around the chip periphery; the band has an inner edge near the chip periphery, and an outer edge near the contour of the polymer protrusion. This metal band serves as a guard ring to stop any nascent crack propagating in the polymer protrusion.

Abstract: Electronic devices of improved reliability having a substrate of electrically insulating material, further an integrated circuit chip with a periphery and a surface. Using a layer of polymeric material, the chip surface is mounted on the substrate surface. The polymeric material protrudes beyond the chip periphery and spreads some distance along the substrate surface. A metal layer is on the substrate surface, this layer is shaped as a band around the chip periphery; the band has an inner edge near the chip periphery, and an outer edge near the contour of the polymer protrusion. This metal band serves as a guard ring to stop any nascent crack propagating in the polymer protrusion.

Abstract: A plastic package for use in semiconductor devices, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each of said terminals. The bumps are made of reflowable metal and have approximately uniform height. An adherent layer of polymer material covers the package surface and surrounds each of the bumps to form a solid meniscus. The layer has a thickness between a quarter and one half of the bump height. An analogous methodology applies to plastic assembly boards.

Abstract: A plastic package for use in semiconductor devices, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each of said terminals. The bumps are made of reflowable metal and have approximately uniform height. An adherent layer of polymer material covers the package surface and surrounds each of the bumps to form a solid meniscus. The layer has a thickness between a quarter and one half of the bump height. An analogous methodology applies to plastic assembly boards.

Abstract: Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.