Abstract: A semiconductor device includes a gate structure over a substrate. The device further includes an isolation feature in the substrate and adjacent to an edge of the gate structure. The device also includes a spacer overlying a sidewall of the gate structure. The spacer has a bottom lower than a top surface of the substrate.

Abstract: Methods and devices for forming a contact over a metal gate for a transistor are provided. The device may comprise an active area, an isolation area surrounding the active area, and a metal gate above the isolation area, wherein the metal gate comprises a conductive layer. The contact comprises a first contact part within the conductive layer, above the isolation area without vertically overlapping the active area, and a second contact part above the first contact part, connected to the first contact part, and substantially vertically contained within the first contact part.

Abstract: Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess. The improved thickness uniformity in turn improves the uniformity of device performance.

Abstract: Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess. The improved thickness uniformity in turn improves the uniformity of device performance.

Abstract: A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.

Abstract: A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.

Abstract: A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations. The method for forming the structure utilizes processing operations and materials used in the formation of the CMOS integrated circuit device.

Abstract: A method for etching a dielectric material in a semiconductor device is disclosed. After providing a conductive region, a dielectric layer is formed over the conductive region. A dielectric antireflective coating (DARC) layer is further formed on the dielectric layer. Then, a moisture-removal step is performed that removes moisture from the DARC layer and from an interface region between the dielectric and the DARC layer. A masking pattern is transferred into the DARC layer and the dielectric layer.

Abstract: A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations. The method for forming the structure utilizes processing operations and materials used in the formation of the CMOS integrated circuit device.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: The present invention provides a method for forming and etching a resist protect oxide layer, of which provides improved etch selectivity to a shallow trench isolation and an increased pre-metal dip processing window. The process begins by forming a shallow trench isolation on a semiconductor substrate. The semiconductor substrate has a first area and a second area separated by the shallow trench isolation. A gate is formed on the semiconductor substrate in the first area, adjacent to the shallow trench isolation. In a key step, a resist protect oxide layer comprising a thin silicon oxide layer and an overlying thin nitrogen containing layer, is deposited over the semiconductor substrate, the gate, and the shallow trench isolation. The thin nitrogen containing layer can be composed of silicon nitride or silicon oxynitride.

Abstract: A method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers during subsequent processing thereby reducing junction depletion and source to drain leakage. The process begins by providing a substrate structure having a gate thereon. Sidewall spacers are formed on the sidewalls of the gate. Impurity ions are implanted into the substrate structure adjacent to the gate to form source and drain regions. A resist protect oxide layer is formed over the substrate structure. The resist protect oxide is patterned by forming a mask over the resist protect oxide layer having an opening over the gate and the source and drain regions. The resist protect oxide layer is selectively etched; thereby removing the resist protect oxide over the source and drain regions without distorting the sidewall spacers. A silicide region is formed on the source and drain regions using a salicide process comprising a pre-amorphous implant and one or more rapid thermal anneal steps.

Abstract: A new method is provided for the formation of silicided layers over points of electrical contact that are required in MOSFET devices. The structure of the MOSFET gate electrode is formed, including LDD regions, gate spacers and source/drain regions. A layer of Resist Protective Oxide (RPO) is deposited over the structure and patterned leaving the RPO in place where the silicided layers are not to be formed and exposing surfaces on which salicided layers are to be formed. These surfaces are the surfaces of the substrate overlying the source and drain regions and the surface of the gate electrode. An extra As or BF2 implant is performed into the surface of the exposed regions after which the process of salicidation is performed following conventional processing steps.

Abstract: This invention provides a method for forming a self-aligned silicide with low sheet resistance in the N+ source and drain regions and the N+ polysilicon regions in a semiconductor device using a titanium nitride barrier layer to prevent nitridation of an underlying titanium layer during rapid thermal anneal. The process begins by providing a substrate structure having a gate thereon. A titanium layer is deposited over the substrate structure and the gate. Mixing ions are implanted through the titanium layer into source and drain regions adjacent to the gate. A titanium nitride barrier layer is deposited on the titanium layer. The substrate structure is rapid thermal annealed causing the titanium layer to react with the underlying silicon to form silicide. The substrate structure is selectively etched to remove the titanium nitride barrier layer and unreacted titanium. A second rapid thermal anneal is performed.

Abstract: A method for forming a polycide layer wherein the silicide layer is blanket deposited over a polysilicon layer and selectively ion implanted through a mask to form regions of a higher resistivity than the masked regions. The implanted polycide layer is then annealed by RTA and patterned to form the conductors, gate electrodes and interconnects from the low resistivity regions and resistive components of an integrated circuit from the high resistivity regions. The capability of selecting from high and low resistive regions in a single polycide layer permits the design of resistive components with smaller areas than would be permitted if the resistive components were formed of a single low resistivity layer. This extra degree of freedom permits the designer to optimize device density and device performance without compromising either. The procedure utilizes a additional masking step utilizing a block-out mask.

Abstract: A method of forming a semiconductor device includes forming of layers of polysilicon and dielectric layers in manufacturing a semiconductor device and patterning the layers into devices using phototlithography and etching process steps. End point mode detection is used in the etching process in a way in which the area exposed during etching is increased to enhance the end point detection capacity, by adding a surplus pad area before pad formation. Specifically an EPROM device is formed with a first level of polysilicon above a gate oxide layer patterned into a floating gate electrode of an EPROM device. Then form an ONO layer above the floating gate electrode. Define array protection, grow a second gate oxide layer, deposit a second level of polysilicon, define peripheral gates from the second level of polysilicon, and define an EPROM transistor gate electrode from the second level of polysilicon.

Abstract: A process has been developed in which a capacitor structure can be simultaneously fabricated with NFET and PFET devices, to be used in EEPROM, SRAM or DRAM cells. The process features the use of a silicon nitride layer, protecting an underlying capacitor dielectric layer from an oxidation ambient, presented during a subsequent NFET source and drain drive-in procedure.