Patents by Inventor Tzu-Chieh Chen
Tzu-Chieh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11988817Abstract: An optical imaging system includes five lens elements, the five lens elements being, in order from an object side to an image side: a first lens element having positive refractive power; a second lens element having negative refractive power; a third lens element having positive refractive power; a fourth lens element having positive refractive power; and a fifth lens element having negative refractive power.Type: GrantFiled: June 1, 2023Date of Patent: May 21, 2024Assignee: LARGAN PRECISION CO., LTD.Inventors: Chien-Hsun Wu, Tzu-Chieh Kuo, Kuan-Ming Chen
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Publication number: 20240161818Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.Type: ApplicationFiled: November 30, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Li-Ping Huang, Yu-Fang Chen, Chun-Yen Tseng, Tzu-Feng Chang, Chun-Chieh Chang
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Patent number: 11971609Abstract: A photographing optical system includes eight lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element and an eighth lens element. The eight lens elements each have an object-side surface facing toward the object side and an image-side surface facing toward the image side. The first lens element has positive refractive power. The fifth lens element has positive refractive power. The object-side surface of the seventh lens element is convex in a paraxial region thereof. The image-side surface of the eighth lens element is concave in a paraxial region thereof. At least one lens surface of at least one lens element of the photographing optical system has at least one critical point in an off-axis region thereof.Type: GrantFiled: March 15, 2022Date of Patent: April 30, 2024Assignee: LARGAN PRECISION CO., LTD.Inventors: Chun-Yen Chen, Kuan-Ting Yeh, Tzu-Chieh Kuo
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Patent number: 11964881Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.Type: GrantFiled: July 27, 2020Date of Patent: April 23, 2024Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
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Publication number: 20240105515Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventors: Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
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Publication number: 20240103378Abstract: The present disclosure provides an extreme ultraviolet (EUV) lithography system including a radiation source and an EUV control system integrated with the radiation source. The EUV control system includes a 3-dimensional diagnostic module (3DDM) designed to collect a laser beam profile of a laser beam from the radiation source in a 3-dimensional (3D) mode, an analysis module designed to analyze the laser beam profile, a database designed to store the laser beam profile, and an EUV control module designed to adjust the radiation source. The analysis module is coupled with the database and the EUV control module. The database is coupled with the 3DDM and the analysis module. The EUV control module is coupled with the analysis module and the radiation source.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Tai-Yu CHEN, Tzu-Jung PAN, Kuan-Hung CHEN, Sheng-Kang YU, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
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Patent number: 11938405Abstract: An electronic device and a method for detecting abnormal device operation are provided. The method includes: obtaining multiple action events of a movable input device, and each action event including a relative coordinate and a time stamp of the movable input device; generating multiple absolute coordinates based on the relative coordinate of each action event; estimating multiple speed vectors based on the absolute coordinates and the time stamp of each action event; estimating multiple acceleration vectors based on the speed vectors and the time stamp of each action event; and estimating a probability of abnormal operation based on the speed vectors and the acceleration vectors.Type: GrantFiled: November 8, 2022Date of Patent: March 26, 2024Assignee: Acer IncorporatedInventors: Tien-Yi Chi, Wei-Chieh Chen, Shih-Cheng Huang, Tzu-Lung Chuang
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Patent number: 11923252Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.Type: GrantFiled: January 27, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
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Patent number: 11914789Abstract: The embodiments of the disclosure provide a method for inputting letters, a host, and a computer readable storage medium. The method includes: in response to determining that a first hand is presented as a first gesture, showing at least one letter set; in response to determining that the first hand has been changed from the first gesture to a second gesture corresponding to a first letter set among the at least one letter set, showing a subset of the first letter set, wherein the subset of the first letter set comprises at least one letter; in response to determining that a first letter among the at least one letter of the subset of the first letter set has been chosen, inputting the first letter.Type: GrantFiled: June 17, 2022Date of Patent: February 27, 2024Assignee: HTC CorporationInventors: Ching-Chun Chen, Tzu-Chieh Yu
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Patent number: 11877433Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).Type: GrantFiled: July 16, 2020Date of Patent: January 16, 2024Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
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Patent number: 11799012Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.Type: GrantFiled: September 4, 2020Date of Patent: October 24, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
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Publication number: 20220130839Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.Type: ApplicationFiled: January 6, 2022Publication date: April 28, 2022Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pin-Hong Chen, Yi-Wei Chen, Tzu-Chieh Chen, Chih-Chieh Tsai, Chia-Chen Wu, Kai-Jiun Chang, Yi-An Huang, Tsun-Min Cheng
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Patent number: 11251187Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.Type: GrantFiled: September 22, 2017Date of Patent: February 15, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pin-Hong Chen, Yi-Wei Chen, Tzu-Chieh Chen, Chih-Chieh Tsai, Chia-Chen Wu, Kai-Jiun Chang, Yi-An Huang, Tsun-Min Cheng
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Patent number: 11239243Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.Type: GrantFiled: May 5, 2020Date of Patent: February 1, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
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Patent number: 11239241Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.Type: GrantFiled: September 26, 2019Date of Patent: February 1, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pin-Hong Chen, Yi-Wei Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Tsun-Min Cheng, Chi-Mao Hsu
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Patent number: 11222784Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.Type: GrantFiled: March 27, 2020Date of Patent: January 11, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
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Patent number: 11088023Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.Type: GrantFiled: March 21, 2018Date of Patent: August 10, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pin-Hong Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Tsun-Min Cheng, Yi-Wei Chen, Wei-Hsin Liu
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Publication number: 20200403077Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
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Publication number: 20200350317Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).Type: ApplicationFiled: July 16, 2020Publication date: November 5, 2020Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
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Patent number: 10804365Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.Type: GrantFiled: May 22, 2018Date of Patent: October 13, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu