Patents by Inventor Tzu-Chieh Chen

Tzu-Chieh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180350673
    Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.
    Type: Application
    Filed: March 21, 2018
    Publication date: December 6, 2018
    Inventors: Pin-Hong Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Tsun-Min Cheng, Yi-Wei Chen, Wei-Hsin Liu
  • Publication number: 20180337187
    Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
    Type: Application
    Filed: July 5, 2018
    Publication date: November 22, 2018
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Publication number: 20180301458
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: March 15, 2018
    Publication date: October 18, 2018
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 10043811
    Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 7, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Publication number: 20180190662
    Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following. A hard mask layer is formed on a metal stack by a chemical vapor deposition process importing nitrogen (N2) gases and then importing amonia (NH3) gases. The present invention also provides a bit line gate structure of a dynamic random access memory (DRAM) including a metal stack and a hard mask. The metal stack includes a polysilicon layer, a titanium layer, a titanium nitride layer, a first tungsten nitride layer, a tungsten layer and a second tungsten nitride layer stacked from bottom to top. The hard mask is disposed on the metal stack.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 5, 2018
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Mei-Ling Chen, Chia-Lung Chang, Ching-Hsiang Chang, Jui-Min Lee, Tsun-Min Cheng, Lin-Chen Lu, Shih-Fang Tzou, Kai-Jiun Chang, Chih-Chieh Tsai, Tzu-Chieh Chen, Chia-Chen Wu
  • Patent number: 9953982
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in a substrate; removing part of the STI to form a first trench; forming a cap layer in the first trench; forming a mask layer on the cap layer and the substrate; and removing part of the mask layer, part of the cap layer, and part of the STI to form a second trench.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 24, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen
  • Patent number: 9859123
    Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having a conductive region is provided. A metal layer is deposited on the conductive region. The metal layer reacts with the conductive region to form a first metal silicide layer. A TiN layer is deposited on the metal layer. A SiN layer is deposited on the TiN layer. An annealing process is performed to convert the first metal silicide layer into a second metal silicide layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: January 2, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Chen Wu, Pin-Hong Chen, Kai-Jiun Chang, Yi-An Huang, Chih-Chieh Tsai, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen
  • Patent number: 9082723
    Abstract: A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: July 14, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Tzu-Chieh Chen, Shih-Chao Chiu, Chia-Cheng Chen
  • Publication number: 20150155250
    Abstract: A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility.
    Type: Application
    Filed: December 30, 2013
    Publication date: June 4, 2015
    Applicant: Siliconware Precision Industries Co., Ltd
    Inventors: Tzu-Chieh Chen, Shih-Chao Chiu, Chia-Cheng Chen