Patents by Inventor Tzu-Yin Chiu
Tzu-Yin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10784296Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The image sensor includes: a semiconductor substrate; a first active region located on the semiconductor substrate; a doped semiconductor layer located on the first active region; and a contact located on the semiconductor layer, where the first active region includes: a first doped region and a second doped region abutting against the first doped region, wherein the second doped region is located at an upper surface of the first active region, and wherein the second doped region is formed by dopants in the semiconductor layer that are annealed to be diffused to a surface layer of the first doped region. The present disclosure may reduce leakage current and improve device performances.Type: GrantFiled: April 23, 2019Date of Patent: September 22, 2020Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International CorporationInventors: Tzu Yin Chiu, Chong Wang, Haifang Zhang, Xuanjie Liu
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Publication number: 20200243206Abstract: A method for nuclide bombardment for neutron generation includes providing a nuclide bombardment target. The target has a metallic single-crystalline layer including a metallic element, the single-crystalline layer including lattice channels disposed of therein, and isotopes of a first element, configured as interstitial elements in the lattice channels in the single-crystalline layer. The method also includes positioning the metallic single-crystalline layer with respect to a bombardment apparatus, such that the bombardment apparatus is configured for injecting particles into the metallic single-crystalline layer substantially along the lattice channels of the single crystalline lattice. The method further includes injecting isotopes of a second element into the metallic single-crystalline layer substantially along the direction of the lattice channels, thereby increasing neutron generation.Type: ApplicationFiled: January 28, 2020Publication date: July 30, 2020Inventor: Tzu-Yin Chiu
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Patent number: 10629646Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The method includes: providing a semiconductor structure, where the semiconductor structure includes: a semiconductor substrate, and a first active region located on the semiconductor substrate, the first active region including a first doped region and a second doped region abutting against the first doped region, and the second doped region being located at an upper surface of the first active region; forming a semiconductor layer on an upper surface of the second doped region; and forming a contact connected to the semiconductor layer. The present disclosure enables defects or damages caused when forming the contact to be kept away from a junction field formed by the second doped region and the first doped region. Therefore, leakage current may be reduced and device performances may be improved.Type: GrantFiled: November 22, 2017Date of Patent: April 21, 2020Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International CorporationInventors: Tzu Yin Chiu, Chong Wang, Haifang Zhang, Xuanjie Liu
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Patent number: 10411018Abstract: Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.Type: GrantFiled: May 12, 2016Date of Patent: September 10, 2019Assignee: Semiconductor Manufacturing International Corp.Inventors: Tzu-Yin Chiu, Juilin Lu, Jianxiang Cai
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Publication number: 20190252422Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The image sensor includes: a semiconductor substrate; a first active region located on the semiconductor substrate; a doped semiconductor layer located on the first active region; and a contact located on the semiconductor layer, where the first active region includes: a first doped region and a second doped region abutting against the first doped region, wherein the second doped region is located at an upper surface of the first active region, and wherein the second doped region is formed by dopants in the semiconductor layer that are annealed to be diffused to a surface layer of the first doped region. The present disclosure may reduce leakage current and improve device performances.Type: ApplicationFiled: April 23, 2019Publication date: August 15, 2019Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Tzu Yin CHIU, Chong Wang, Haifang Zhang, Xuanjie Liu
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Patent number: 10062704Abstract: A method is provided for fabricating a buried-channel MOSFET and a surface-channel MOSFET of the same type and different gate electrodes on a same wafer. The method includes providing a semiconductor substrate having a well area and a plurality of shallow trench isolation structures; forming a threshold implantation region doped with impurity ions opposite of that of the well area in the well area for the buried-channel MOSFET; forming a gate structure including a gate dielectric layer and a gate electrode on the semiconductor substrate, wherein the gate electrode of the buried-channel MOSFET is doped with impurity ions with a same type as that of the well area, and the gate electrode of the surface-channel MOSFET is doped with impurity ions with a type opposite of that of the well area; and forming source and drain regions in the semiconductor substrate at both sides of the gate structure.Type: GrantFiled: December 29, 2016Date of Patent: August 28, 2018Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Tzu Yin Chiu, Clifford Ian Drowley, Leong Tee Koh, Yu Lei Jiang, Da Qiang Yu
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Publication number: 20180175082Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The image sensor includes: a semiconductor substrate; a first active region located on the semiconductor substrate; a doped semiconductor layer located on the first active region; and a contact located on the semiconductor layer, where the first active region includes: a first doped region and a second doped region abutting against the first doped region, wherein the second doped region is located at an upper surface of the first active region, and wherein the second doped region is formed by dopants in the semiconductor layer that are annealed to be diffused to a surface layer of the first doped region. The present disclosure may reduce leakage current and improve device performances.Type: ApplicationFiled: November 22, 2017Publication date: June 21, 2018Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Tzu Yin Chiu, Chong Wang, Haifang Zhang, Xuanjie Liu
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Publication number: 20180175098Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The method includes: providing a semiconductor structure, where the semiconductor structure includes: a semiconductor substrate, and a first active region located on the semiconductor substrate, the first active region including a first doped region and a second doped region abutting against the first doped region, and the second doped region being located at an upper surface of the first active region; forming a semiconductor layer on an upper surface of the second doped region; and forming a contact connected to the semiconductor layer. The present disclosure enables defects or damages caused when forming the contact to be kept away from a junction field formed by the second doped region and the first doped region. Therefore, leakage current may be reduced and device performances may be improved.Type: ApplicationFiled: November 22, 2017Publication date: June 21, 2018Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Tzu Yin Chiu, Chong Wang, Haifang Zhang, Xuanjie Liu
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Publication number: 20170194339Abstract: A method is provided for fabricating a buried-channel MOSFET and a surface-channel MOSFET of the same type and different gate electrodes on a same wafer. The method includes providing a semiconductor substrate having a well area and a plurality of shallow trench isolation structures; forming a threshold implantation region doped with impurity ions opposite of that of the well area in the well area for the buried-channel MOSFET; forming a gate structure including a gate dielectric layer and a gate electrode on the semiconductor substrate, wherein the gate electrode of the buried-channel MOSFET is doped with impurity ions with a same type as that of the well area, and the gate electrode of the surface-channel MOSFET is doped with impurity ions with a type opposite of that of the well area; and forming source and drain regions in the semiconductor substrate at both sides of the gate structure.Type: ApplicationFiled: December 29, 2016Publication date: July 6, 2017Inventors: Tzu Yin CHIU, Clifford Ian DROWLEY, Leong Tee KOH, Yu Lei JIANG, Da Qiang YU
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Publication number: 20160260720Abstract: Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.Type: ApplicationFiled: May 12, 2016Publication date: September 8, 2016Inventors: TZU-YIN CHIU, JUILIN LU, JIANXIANG CAI
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Patent number: 9368503Abstract: Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.Type: GrantFiled: May 9, 2013Date of Patent: June 14, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.Inventors: Tzu-Yin Chiu, Juilin Lu, Jianxiang Cai
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Publication number: 20160078970Abstract: A method for nuclide bombardment includes providing a nuclide bombardment target, which includes a metallic single-crystalline layer having a hydrogen-absorbing metallic element. The single-crystalline layer includes lattice channels disposed therein. The target also includes first hydrogen isotopes, configured as interstitial elements in the lattice channels in the single-crystalline layer. The method further includes injecting second hydrogen isotopes into the target substantially along the direction of the lattice channels.Type: ApplicationFiled: September 9, 2015Publication date: March 17, 2016Inventor: Tzu-Yin CHIU
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Patent number: 9263548Abstract: A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.Type: GrantFiled: January 13, 2015Date of Patent: February 16, 2016Inventor: Tzu-Yin Chiu
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Publication number: 20150194500Abstract: A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.Type: ApplicationFiled: January 13, 2015Publication date: July 9, 2015Inventor: Tzu-Yin Chiu
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Patent number: 8936989Abstract: A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.Type: GrantFiled: April 10, 2008Date of Patent: January 20, 2015Inventor: Tzu-Yin Chiu
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Patent number: 8828854Abstract: A method of introducing dopants into a semiconductor wafer includes implanting the dopants into a region below a surface of the semiconductor wafer using an ion beam to form a first implanted layer. The dopants when activated causing a conductivity of the implanted layer to be either of N-type or P-type. The first implanted layer is characterized by a peak dopant concentration at a first depth below the surface of the semiconductor wafer. The method also includes removing a layer from the semiconductor wafer surface, wherein said layer includes a portion of said dopants.Type: GrantFiled: February 22, 2013Date of Patent: September 9, 2014Inventor: Tzu-Yin Chiu
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Patent number: 8816449Abstract: An integrated circuit structure has a substrate comprising a well region and a surface region, an isolation region within the well region, a gate insulating layer overlying the surface region, first and second source/drain regions within the well region of the substrate. The structure also has a channel region formed between the first and second source/drain regions and within a vicinity of the gate insulating layer, and a gate layer overlying the gate insulating layer and coupled to the channel region. The structure has sidewall spacers on edges of the gate layer to isolate the gate layer, a local interconnect layer overlying the surface region of the substrate and having an edge region extending within a vicinity of the first source/drain region. A contact layer on the first source/drain region in contact with the edge region and has a portion abutting a portion of the sidewall spacers.Type: GrantFiled: September 17, 2013Date of Patent: August 26, 2014Assignees: Semiconductor Manufacturing International (Shanghai) Corp., Semiconductor Manufacturing International (Beijing) Corp.Inventor: Tzu-Yin Chiu
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Publication number: 20140103445Abstract: Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.Type: ApplicationFiled: May 9, 2013Publication date: April 17, 2014Applicant: Semiconductor Manufacturing International Corp.Inventors: TZU-YIN CHIU, JUILIN LU, JIANXIANG CAI
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Publication number: 20140048892Abstract: An integrated circuit structure has a substrate comprising a well region and a surface region, an isolation region within the well region, a gate insulating layer overlying the surface region, first and second source/drain regions within the well region of the substrate. The structure also has a channel region formed between the first and second source/drain regions and within a vicinity of the gate insulating layer, and a gate layer overlying the gate insulating layer and coupled to the channel region. The structure has sidewall spacers on edges of the gate layer to isolate the gate layer, a local interconnect layer overlying the surface region of the substrate and having an edge region extending within a vicinity of the first source/drain region. A contact layer on the first source/drain region in contact with the edge region and has a portion abutting a portion of the sidewall spacers.Type: ApplicationFiled: September 17, 2013Publication date: February 20, 2014Applicants: Semiconductor Manufacturing International (Bejing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventor: TZU-YIN CHIU
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Patent number: 8598004Abstract: A method for fabricating a semiconductor integrated circuit and resulting structure. The method includes providing a semiconductor substrate with an overlying dielectric layer and forming a polysilicon gate layer and an overlying capping layer. The gate layer is overlying the dielectric layer. The method also includes patterning the polysilicon gate layer to form a gate structure and a local interconnect structure. The gate structure and the local interconnect structure include a contact region defined therebetween. The gate structure also includes the overlying capping layer. The method includes forming sidewall spacers on the gate structure and the local interconnect structure and removing the sidewall spacer on the local interconnect structure. The method also includes forming contact polysilicon on the contact region and implanting a dopant impurity into the contact polysilicon.Type: GrantFiled: October 24, 2008Date of Patent: December 3, 2013Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Tzu Yin Chiu